http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021082695-A1

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filingDate 2019-09-17^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cd34adba8e01d1d29211cab171069f8e
publicationDate 2021-03-18^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2021082695-A1
titleOfInvention Method for isolating gates in transistors
abstract A method of forming an electrically insulating barrier between a source contact and a drain contact of a transistor device including an electrically insulating layer disposed atop a semi-conductive layer, and an electrically conductive layer disposed atop the electrically insulating layer, the source contact and the drain contact extending from the electrically conductive layer through the electrically insulating layer to the semi-conductive layer, the method including disposing a hardmask layer atop the electrically conductive layer, disposing a photoresist layer atop the hardmask layer, performing a photolithography process to form a trench in the hardmask layer to expose an underlying portion of the electrically conductive layer spanning between the source contact and the drain contact, and performing an ion implantation process, wherein an ion beam formed of ionized oxygen atoms is directed into the trench to oxidize the exposed portion of the electrically conductive layer.
priorityDate 2019-09-17^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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