http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021097013-A1

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filingDate 2019-09-27^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b3587d7d91add091872fbe00b6adfba8
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publicationDate 2021-04-01^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2021097013-A1
titleOfInvention Active bridge chiplet with integrated cache
abstract A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via an active bridge chiplet. The active bridge chiplet is an active silicon die that bridges GPU chiplets and allows partitioning of systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.
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priorityDate 2019-09-27^^<http://www.w3.org/2001/XMLSchema#date>
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