Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b6caea61bfde8a45e01a8deabff80d97 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-50 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1157 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11582 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11565 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-27 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11519 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-46 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-35 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-27 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-40 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-35 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11524 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11539 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11556 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11539 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11582 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11556 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11565 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-1157 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11519 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11524 |
filingDate |
2020-06-05^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e402f3ceec92b88bd701da611f487e0b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_14b0e59d3af82306f5416d0598ccc7b0 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_554f364b331d82a70e2f1bc87c8b7148 |
publicationDate |
2021-12-09^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-2021384206-A1 |
titleOfInvention |
Three-dimensional memory device including through-memory-level via structures and methods of making the same |
abstract |
A three-dimensional memory device can include at least one alternating stack of insulating layers and electrically conductive layers located over a semiconductor material layer, memory stack structures vertically extending through the at least one alternating stack, and a vertical stack of dielectric plates interlaced with laterally extending portions of the insulating layers of the at least one alternating stack. A conductive via structure can vertically extend through each dielectric plate and the insulating layers, and can contact an underlying metal interconnect structure. Additionally or alternatively, support pillar structures can vertically extend through the vertical stack of dielectric plates and into an opening through the semiconductor material layer, and can contact lower-level dielectric material layers embedding the underlying metal interconnect structure to enhance structural support to the three-dimensional memory device during manufacture. |
priorityDate |
2020-06-05^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |