| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_df0d6684067f3028fa0c90119c7f27b8 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S148-072
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S148-065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S148-011 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7787
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66863
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-808
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76885
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7371
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28575 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-285
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-72
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-737
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-338
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-778
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-80
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-335
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-808 |
| filingDate |
1987-03-26^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
1991-01-01^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9e4eb7a2dd8843dbcb6664d33f40aee8 |
| publicationDate |
1991-01-01^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-4981808-A |
| titleOfInvention |
Process for the manufacture of III-V semiconductor devices |
| abstract |
A process for the manufacture of a transistor device of the type having active regions e.g. an emitter (17) and a base (11) each contacted by isolated extended conductive regions (37, 33) respectively. At start of process a mesa structure is defined in layered III-V material (3, 5, 11 and 13). The sidewall of the mesa is covered by a conformal coating (27) of insulating material; and, lattice matched material (33) grown on the exposed adjacent material (25) to form a first extended contact. This then is covered by a further layer (35) of insulating material (35). The second extended contact (37) is then grown over the mesa active region material (13). This contact material (37) is isolated from the first contact material (33) by the remanent insulating material (27, 35). This process is applicable to the GaAs/GaAlAs III-V material system as also other material systems. Transistor devices produced by this process may be either bipolar or field-effect type. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8946032-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5391504-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5187109-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5364816-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2013017657-A1 |
| priorityDate |
1986-03-27^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |