| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_44b794f45a97beee610b7de33cd0503b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_80787665b837ed3eb503bbcd27c0043a |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1042
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1072
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1006 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F17-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 |
| filingDate |
1999-10-06^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2000-08-01^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_142a9d364b853416f9bda11124bf71a0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_be3cb0883ab10a880bee0685467a0059
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d684bf6b456d7232b6c34bcd87f6c6e2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d9d0546e68e0fda1fa4346c79902672d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_359853ea7ca0884b1dce6f91d0e0d18f |
| publicationDate |
2000-08-01^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-6097663-A |
| titleOfInvention |
Semiconductor IC device having a memory and a logic circuit implemented with a single chip |
| abstract |
A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module. In the bank module are arranged row-system circuits which operate independently of each other and a multiplicity of I/O lines which extend in a bit line direction. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6542426-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7999594-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2009003027-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2010019823-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7864555-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6310816-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6496440-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6658544-B2 |
| priorityDate |
1996-03-08^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |