http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6258437-B1

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filingDate 1999-03-31^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2001-07-10^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d902aba918f04ebda56fe09982699a63
publicationDate 2001-07-10^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-6258437-B1
titleOfInvention Test structure and methodology for characterizing etching in an integrated circuit fabrication process
abstract A test structure for characterizing etching procedures used in integrated circuit fabrication processes and a method for using the test structure are described. The test structure includes a contrast layer, a simulated substrate, and a pattern layer arranged in order upon a substrate. The simulated substrate includes portions mimicking a semiconductor substrate and portions mimicking isolation regions. Etching of the pattern layer may be performed according to a procedure used in the fabrication of integrated circuits. The contrast layer may be selectively etched relative to the substrate, the simulated substrate, and the pattern layer. Exposure of the etched test structure to a wet etchant selective for the contrast layer may be used to identify defects resulting from over-etching or other errors in the integrated circuit fabrication procedure being tested.
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