http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6300655-B1

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e5db580deca7130dbe51805c6c608b35
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-0335
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-488
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242
filingDate 1999-03-10^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2001-10-09^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_91d5719140e365b7e3de67a15dac1532
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2783e49d2cdc0691fc0f52fcc953bda9
publicationDate 2001-10-09^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-6300655-B1
titleOfInvention Semiconductor memory of good retention and its manufacture
abstract A plurality of memory cell transistors are formed on a principal surface of a semiconductor substrate in a plurality of active regions defined by an isolation region. Each memory cell transistor uses one word line as its gate electrode and has a pair of source and drain regions defined by the gate electrode and the isolation region. One of a pair of source and drain regions is connected to one of a plurality of bit lines, and the other region is connected to one of a plurality of capacitors. Three sides of the other region are defined by the isolation region. The other region includes a first impurity doped region extending to under another word line adjacent to the one word line and a second impurity doped region partially overlapping the first impurity doped region and the gate electrode.
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priorityDate 1998-03-12^^<http://www.w3.org/2001/XMLSchema#date>
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