http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6369608-B1

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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-17792
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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-177
filingDate 2001-01-18^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2002-04-09^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d591094abbbf5cfcd9e9396309c0523d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f533f547cbb37410767c1c8dbc925d93
publicationDate 2002-04-09^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-6369608-B1
titleOfInvention Conditioning semiconductor-on-insulator transistors for programmable logic devices
abstract Method and apparatus for preconditioning and in-use conditioning of transistors formed on a semiconductor-on-insulator structure is described. More particularly, transistors of a programmable logic device (PLD), such as a field programmable gate array (FPGA), are preconditioned to take advantage of charge accumulation owing to a “floating body” effect. This preconditioning takes a form of switching transistors on and off prior to customer operation. Accordingly, semiconductor-on-insulator transistors accumulate charge during this switching period, so when customer operation takes place, transistor switching times are less variable over a period of operation of the PLD. Additionally, a design process and implementation is described for identification and in-use conditioning of transistors that may need conditioning during customer operation to control switching time variability.
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priorityDate 2001-01-18^^<http://www.w3.org/2001/XMLSchema#date>
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