| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6a6c760472ee4c29e9cd26152ace2eb0 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6684
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78391 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8246
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate |
2000-01-12^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2002-10-08^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_aa9e06d3fd3d084867f579d850553b3c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c173beab7da4ee3a76d53501fd4466b2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_999c7b768b0de454f7826b7095ccdb85
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2aba0fcbe2b65acf175ad259f1957315 |
| publicationDate |
2002-10-08^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-6462366-B1 |
| titleOfInvention |
Ferroelectric nonvolatile transistor |
| abstract |
A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of δ, includes preparing a silicon substrate for construction of a ferroelectric gate unit; implanting boron ions to form a p-well in the substrate; isolating plural device areas on the substrate; forming a FE gate stack surround structure; etching the FE gate stack surround structure to form an opening having a width of L 1 to expose the substrate in a gate region; depositing oxide to a thickness of between about 10 nm to 40 nm over the exposed substrate; forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L 2, wherein L 2 ≧L 1+ 2δ; depositing a first insulating layer over the structure; implanting arsenic or phosphorous ions to form a source region and a drain region; annealing the structure; depositing a second insulating layer; and metallizing the structure. n A ferroelectric memory transistor includes a silicon substrate having a p-well formed therein; a gate region, a source region and a drain region disposed along the upper surface of said substrate; a FE gate stack surround structure having an opening having a width of L 1 located about said gate region; a FE gate stack formed in said FE gate stack surround structure, wherein said FE gate stack has a width of L 2, wherein L 2 ≧L 1 +2δ, wherein δ is the alignment tolerance of the lithographic process. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6784473-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2004137675-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2004147086-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011084323-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7118976-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7393785-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2002146902-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2005006689-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2005260823-A9
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7226861-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2002149042-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9773793-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6750501-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7217970-B2 |
| priorityDate |
1998-11-05^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |