| abstract |
The invention provides an ASIC architecture that incorporates an SSCG module therein and that utilizes both a frequency modulated clock signal and a pure clock signal, where both clock signals are substantially synchronized and where the ASIC architecture minimizes the number of pins and silicon area needed to provide the dual clock signals. Additionally, because the clock signals are derived from the same externally generated clock signal and are received into the ASIC through the same clock input buffer, the clock signals on both branch paths will be substantially synchronized, thereby reducing drift, skew or delay errors in the clock I/O buffers, between the various sections of the integrated circuit and/or between the various components coupled to, or part of the electronic device in which the integrated circuit is a part. |