| abstract |
A digital parallel multiplier has encoders for each segmented bit pair of the multiplier input data which select one of 4 coefficients, based on the sum of the bit pair, that are then applied to the multiplicand input data. The addition of the rows of the scaled multiplicand input data is performed with adders with two data inputs (plus carryin). These adders are cascaded such that normally invalid data ripples through the adder before the final result is achieved. By controlling the time power is applied to the adders most of the intermediate states are eliminated. |