http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6720210-B1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_aea8583efc4aa4e2a9706d789804d37b |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B20-383 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B20-367 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B20-00 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-112 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8246 |
| filingDate | 2002-10-17^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2004-04-13^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1342d1a7d1ec8156c598ec16db25a1a2 |
| publicationDate | 2004-04-13^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-6720210-B1 |
| titleOfInvention | Mask ROM structure and manufacturing method thereof |
| abstract | A mask read-only-memory structure and its method of manufacture are provided. The structure includes a substrate, a buried bit line in the substrate and a patterned stack layer covering a portion of the upper surface of the substrate. The stack layer includes a first dielectric layer, a stopping layer and a second dielectric layer. A gate oxide layer covers a portion of the upper surface of the substrate. A word line runs across the buried bit line to form a plurality of coding cells. The memory cells having a stack layer thereon are at a logic state “0” while the memory cells having a gate oxide layer thereon are at a logic state “1”. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7084014-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2005074924-A1 |
| priorityDate | 2002-10-17^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
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