| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_283357e4e5b1d2334bd15817360ddd5a |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4076
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1039
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-1615
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1006 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 |
| filingDate |
2004-04-02^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2005-11-08^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d67257f4f4beb55c423d571a0521b87a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ecd64869f090d43a161f97b3c40acaac
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_81f32d20d882f3877dc8c69ab8254d03
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d398baf67b4d0db66ae5f8a950e6b139
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1c53258dbb58a2af8c232f621105f295
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1f026c08fbd4defd902f2a74ce3ddf32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c10b662374a8d589c3a7a23feca32071 |
| publicationDate |
2005-11-08^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-6963956-B2 |
| titleOfInvention |
Apparatus and method for pipelined memory operations |
| abstract |
A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications. |
| priorityDate |
1997-10-10^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |