| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/A45D44-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/A61H2205-022 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28518
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823814
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/A61H23-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/A61N1-30 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-285
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-4763
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-302
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-44
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-461 |
| filingDate |
2005-01-24^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2009-02-03^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9c6dcaa5385065c139fad5b3fdfe9ee2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fd3aedb2a900f39e0052063413345701
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d51b1e3044edeb317442faaf0e5906d6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_326a55a3b45544289f0ebd9f695b6750 |
| publicationDate |
2009-02-03^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-7485558-B2 |
| titleOfInvention |
Method of manufacturing semiconductor device |
| abstract |
In a method of manufacturing a semiconductor device, a preliminary metal silicide layer is selectively formed on a substrate having a transistor, the transistor having source/drain regions. A capping layer having a thermal expansion coefficient greater than that of the preliminary metal silicide layer is formed on the substrate having the preliminary metal silicide layer. The substrate is thermally treated to form a metal silicide layer, and to apply a tensile stress caused by a thermal expansion coefficient difference between the metal silicide layer and the capping layer to the source/drain regions of the transistor. |
| priorityDate |
2004-01-27^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |