| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c3a2f00e72ba6e4c09b6da573427fbed |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76888 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76802
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31144
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0335
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76844
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31116
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0332
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0337
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76831 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-302
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-461
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-033
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-311 |
| filingDate |
2006-08-18^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2009-08-11^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_75ff23cb10cd812b11320b591f03af65
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_457c92be400cfddad54b3978197bac1b |
| publicationDate |
2009-08-11^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-7573116-B2 |
| titleOfInvention |
Etch aided by electrically shorting upper and lower sidewall portions during the formation of a semiconductor device |
| abstract |
A method used to fabricate a semiconductor device comprises etching a dielectric layer, resulting in an undesirable charge buildup along a sidewall formed in the dielectric layer during the etch. The charge buildup along a top and a bottom of the sidewall may reduce the etch rate thereby resulting in excessive etch times and undesirable etch opening profiles. To remove the charge, a sacrificial conductive layer may be formed to electrically short the upper and lower portions of the sidewall and eliminate the charge. In another embodiment, a gas is used to remove the charge. After removing the charge, the dielectric etch may continue. Various embodiments of the inventive process and structures are described. |
| priorityDate |
2001-10-09^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |