| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fbb477cab6287ad715ceb612f63441ba |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318519 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-17764
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-17736 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-00 |
| filingDate |
2008-09-05^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2010-09-28^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_97f8a039f86fd35d77e25abf22d842d3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bea7f145055928c980858ddbd35e1f1a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a30505de241a888ae262759c9b46e87c |
| publicationDate |
2010-09-28^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-7804321-B2 |
| titleOfInvention |
Circuits and methods for testing FPGA routing switches |
| abstract |
An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11671099-B2 |
| priorityDate |
2008-09-05^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |