| abstract |
A method includes forming a patterned buildup layer on a first surface of a dielectric layer, the patterned buildup layer including a patterned buildup layer opening exposing a trace coupled to the dielectric layer. A conductor layer is flash plated on the patterned buildup layer and within the patterned buildup layer opening. The patterned buildup layer opening is filled with a blanket conductive filler layer. The blanket conductive filler layer and the conductor layer are planarized to form a flip chip bump. |