| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e5a942ae3f28b0dc97942620cce0b323
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1e71997f8486cea56ad11757cbe6fb8c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a4d7e99b7e682f0ff3b1d61281aa1d6b |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0922
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-495 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-45
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-456
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7835
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823418
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7816 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-76 |
| filingDate |
2010-08-18^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2013-07-16^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_18fa6198e3cc8378832c65b93ccba77d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3074cb2903abdb71b24c2e125a3b9de3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_24dd4e0a5a26431e2c23da1ab23a225f |
| publicationDate |
2013-07-16^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-8487376-B2 |
| titleOfInvention |
High-voltage transistor architectures, processes of forming same, and systems containing same |
| abstract |
An apparatus includes a first device with a metal gate and a drain well that experiences a series resistance that drops a drain contact voltage from 10 V to 4-6 V at a junction between the drain well and a channel under the gate. The apparatus includes an interlayer dielectric layer (ILD0) disposed above and on the drain well and a salicide drain contact in the drain well. The apparatus also includes a subsequent device that is located in a region different from the first device that operates at a voltage lower than the first device. |
| priorityDate |
2010-08-18^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |