| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d2af4fa54541ffebbf8d9c243383df60
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_992af83428a00793a65b50a559692ccf
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3baaebdc599eccbffc56c764469e366e |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3436
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-38
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1051
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1039
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-1008
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0246 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F3-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-00 |
| filingDate |
2009-01-13^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2013-12-31^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f0af18bb54a609bd1c994b287297011f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_23fd7d302808e5014cadc5f1bc05403e |
| publicationDate |
2013-12-31^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-8621323-B2 |
| titleOfInvention |
Pipelined data relocation and improved chip architectures |
| abstract |
The present invention presents methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior to its being re-written, but diminish or eliminate the additional time penalty this would normally incur. A number of architectural examples are described to facilitate these methods, including: introducing two registers on the memory where each is independently accessible by the controller; allowing a first memory register to be written from while a second register is written to; introducing two registers on the memory where the contents of the registers can be swapped. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2014164682-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10567006-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9489298-B2 |
| priorityDate |
2004-05-13^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |