Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_06c05e948c56b17a4e860947710302fe |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D10-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-324 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-1604 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-085 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-0315 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F21-75 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-08 |
classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-10 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F21-75 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-06 |
filingDate |
2013-12-13^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
2015-02-24^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_27b4d93ad6834284dc563f3056861c5b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d4dced7b8f6fded2b2b353bfab0311c4 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9b771d442b8af846542e8247c8730882 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_90640f9ac14345d6fabbfed6a589306c |
publicationDate |
2015-02-24^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-8963599-B2 |
titleOfInvention |
Multi-frequency clock skew control for inter-chip communication in synchronous digital systems |
abstract |
Embodiments are disclosed of a multi-chip apparatus capable of performing multi-rate synchronous communication between component chips. Each chip may receive a common clock reference signal, and may generate an internal clock signal dependent on the clock reference signal. A clock distribution tree and phase-locked loop may be used to minimize internal clock skew at I/O circuitry at the chip perimeter. Each chip may also generate an internal synchronizing signal that is phase-aligned to the received clock reference signal. Each chip may use its respective synchronizing signal to synchronize multiple clock dividers that provide software-selectable reduced-frequency clock signals to the I/O cells of the chip. In this way, the reduced-frequency clock signals of the multiple chips are edge-aligned to the low-skew internal clock signals, and phase-aligned to the common clock reference signal, allowing the I/O cells of the multiple chips to perform synchronous communication at multiple rates with low clock skew. |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11099601-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-108809569-B http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-108809569-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10698440-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10853304-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9595508-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10901936-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10361175-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9558150-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11275708-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2015160975-A1 |
priorityDate |
2012-12-13^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |