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filingDate 2016-01-07^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2016-12-20^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2016-12-20^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-9523738-B2
titleOfInvention TCK/TMS(C) counter circuitry with third, fourth count and reset outputs
abstract Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state.
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