| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_4ac03beb820d9c788fb05db23dbad9b1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c3a2f00e72ba6e4c09b6da573427fbed
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9f80acb1e5f9480b0d2d11a31b3497da |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-3025
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-09701
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13025
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01079
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01078
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05025
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-12042
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-0401 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-00 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-48 |
| filingDate |
2009-08-21^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2017-10-24^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4a5c49759318ca11cc43404a40fcaea9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_68cb35a4be260c0a9944c462adc10c38 |
| publicationDate |
2017-10-24^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9799562-B2 |
| titleOfInvention |
Vias and conductive routing layers in semiconductor substrates |
| abstract |
Through vias and conductive routing layers in semiconductor substrates and associated methods of manufacturing are disclosed herein. In one embodiment, a method for processing a semiconductor substrate includes forming an aperture in a semiconductor substrate and through a dielectric on the semiconductor substrate. The aperture has a first end open at the dielectric and a second end opposite the first end. The method can also include forming a plurality of depressions in the dielectric, and simultaneously depositing a conductive material into the aperture and at least some of the depressions. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11527436-B2 |
| priorityDate |
2009-08-21^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |