| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42348
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11575
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11565
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11573
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11582
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-27
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-50 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-51
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11575
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11573
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11565
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11582 |
| filingDate |
2016-08-29^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2018-02-13^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_34b5125e3fad981c4c6dc7ec5d1434e9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_99b81eb5461f0bb182e4558aacb55c86
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_32d4ce8b6326adde54956ac6a61c3710
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c7f2e333ea97bd38b3546b510b0411f3 |
| publicationDate |
2018-02-13^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9893082-B2 |
| titleOfInvention |
Semiconductor memory device and method of fabricating the same |
| abstract |
A semiconductor memory device includes a stack including gate electrodes and insulating layers that are alternately and repeatedly stacked on a substrate. A cell channel structure penetrates the stack. The cell channel structure includes a first semiconductor pattern contacting the substrate and a first channel pattern on the first semiconductor pattern. The first semiconductor pattern extends to a first height from a surface of the substrate to a top surface of the first semiconductor pattern. A dummy channel structure on the substrate and spaced apart from the stack. The dummy channel structure includes a second semiconductor pattern contacting the substrate and a second channel pattern on the second semiconductor pattern. The second semiconductor pattern extends to a second height from the surface of the substrate to a top surface of the second semiconductor pattern. The first height is greater than the second height. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10685695-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11411078-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2019259439-A1 |
| priorityDate |
2015-01-30^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |