http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9910827-B2

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filingDate 2016-07-01^^<http://www.w3.org/2001/XMLSchema#date>
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inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_043fdff10662c7fb91bde4280d34c7c7
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publicationDate 2018-03-06^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-9910827-B2
titleOfInvention Vector-matrix multiplications involving negative values
abstract Examples herein relate to circuits for computing vector-matrix multiplications involving negative values. A first memory crossbar array may be mapped to a first matrix which includes the positive values of an input matrix. A second memory crossbar array may be mapped to a second matrix which includes the negative values of the input matrix. An analog-to-digital converter may generate digital intermediate multiplication results based on analog results computed by the memory crossbar arrays. The digital intermediate multiplication results may include an intermediate result corresponding to a multiplication of each of the first vector and second vector with each of the first matrix and the second matrix. A controller may aggregate the digital intermediate results to generate a combined multiple result that represents the vector-matrix multiplication of the input vector and the input matrix.
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