http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-0124031-A2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8a356996a2acce5f149f93fa54c53948 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e118452df2a432707a6bbc962d75db3d http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0aa321b3ecb781e997c817b5c82c831e http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b76d5ffdacc1bd4d495781e52b21e36c http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_02beed5ccba80f2377429e23e87c0056 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ff55786e02efdbb0f66c10edaa9ad2f8 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-17343 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-17381 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-36 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-173 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-177 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-80 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-08 |
| filingDate | 2000-09-29^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9553b05100d3ea49599a8549d12b0ccb http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7f5ebbbfa1d65065e94b5ea453b1af76 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_00b42f634f2d84cfc739c4da12afec18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_46ff0146725c8e7b18d7328487f39b07 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b8e3a99d3da414b9a0d573a1dbc7f66c |
| publicationDate | 2001-04-05^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-0124031-A2 |
| titleOfInvention | Multiprocessor node controller circuit and method |
| abstract | Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip. Optionally, the memory is packaged on plugable memory/directory cards wherein each card includes a plurality of memory chips including a first subset dedicated to holding memory data and a second subset dedicated to holding directory data. Further, the memory port includes a memory data port including a memory data bus and a memory address bus coupled to the first subset of memory chips, and a directory data port including a directory data bus and a directory address bus coupled to the second subset of memory chips. In some such embodiments, the ratio of (memory data space) to (directory data space) on each card is set to a value that is based on a size of the multiprocessor computer system. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-03036508-A3 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-03036508-A2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2008083012-A1 |
| priorityDate | 1999-09-29^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
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