| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_73a7ce7a4956376042c57acac1a79fb9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_717c2eb63e678ec884e169d6578d4e94
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_54735d62e4f69f464580951df9228312
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_bd4cf5ba3798a1084fdcbac9d5c26cb3 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C17-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0466
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0416
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-77
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S257-91
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C17-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-71 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-18 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C17-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C17-12 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L31-0328
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4097
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-06 |
| filingDate |
2004-03-31^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b2e33eb55566652f718b2c9057b5dad3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_31b047342f8717998907e5e5ce0a97e1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3f49a2a314f13095d31bdd6109461415 |
| publicationDate |
2004-10-21^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2004090905-A2 |
| titleOfInvention |
Three-dimensional memory device incorporating segmented bit line memory array |
| abstract |
A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7830722-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7317641-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7764549-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9111800-B2 |
| priorityDate |
2003-03-31^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |