| abstract |
A bit error rate tester (100) for use in connection with a high speed networks. The bit error rate tester (100) includes transmit and receive ports (102, 104, 106 and 108), as well as a sequence generator (302), memory (112), synchronizer (322), sequence start detect module (326), and comparator (338). The sequence generator (302) generates a bit sequence for transmission through a network path. The bit sequence returns to the bit error rate tester (100) by way of the receive port (102, 104, 106 or 108). The synchronizer (322) then bit-aligns the received bit sequence to compensate for idles/fill words added/dropped as the bit sequence transited the network. The synchronized bit sequence is passed to the start word detector (326) which detects start and end words in the bit sequence and instructs the comparator (338) to compare only data between the start and end words. The comparator (338) compares the received bit sequence with a copy of the transmitted bit sequence regenerated from the memory (112), and calculates a bit error rate. |