http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2007037318-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5547f741b25666fc4ae5195cf71a979b http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_24c4e6b8156352f1ee9121ff80abedb5 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L2207-06 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-101 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-087 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11B20-10425 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11B20-1403 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11B20-10055 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11B20-14 |
| filingDate | 2006-09-28^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_527dbe68acaef6bbc1acfe5c1d4c0d1f |
| publicationDate | 2007-04-05^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-2007037318-A1 |
| titleOfInvention | Phase synchronizing device and method, and optical disk device |
| abstract | Provided is a phase synchronizing device having a quickly drawable PLL circuit. When this PLL circuit (17) comes into an asynchronous state, a maximum code inversion interval meter (18) measures the maximum of a code inversion interval in discrimination data outputted by a PRML block (16). A first channel frequency estimator (19) estimates a channel frequency, on the basis of the maximum of the code inversion interval, and outputs an estimated channel frequency fdet_T. The PLL circuit (17) sets the center frequency to the estimated channel frequency fdet_T. After this, a sync interval meter (20) measures a sync interval from the discrimination data. A second channel frequency estimator (21) estimates the channel frequency on the basis of the sync interval measured, and outputs an estimated channel frequency fdet_S, and the PLL circuit (17) sets the center frequency to the estimated channel frequency fdet_S. |
| priorityDate | 2005-09-28^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
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