| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_704bbf830fa4d19de602f1393446f82e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_05bea87a3092bdb31ddcf14ee93a7937
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c186e9ae8cafab5df5c8d80cfa7b0fa1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_63bcd918bf6916a4b4f0a2c1a9f0d494 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1608
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0623
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4236 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1608
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66068
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-049
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7813
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0475
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-36
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-045 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-12 |
| filingDate |
2012-08-03^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0261fdb3ff4206df5241b21a8fba86c3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_54c638f93bea2ce7b683fc36e276eb6b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_66ad0fb0e57d2bb5202bdbdfe7a5ea55 |
| publicationDate |
2013-04-04^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2013046924-A1 |
| titleOfInvention |
Silicon carbide semiconductor device |
| abstract |
A first layer (2) has n-type conductivity. A second layer (3) is a layer that is epitaxially formed on the first layer (2) and has p-type conductivity. A third layer (4) is a layer that is formed on the second layer (3) and has n-type conductivity. When the donor impurity concentration is defined as ND, the acceptor impurity concentration is defined as NA and the position in the depth direction from the interface between the first layer (2) and the second layer (3) toward the first layer (2) is defined as D1, the value of D1 at which 1 ≤ ND/NA ≤ 50 is satisfied is 1 μm or less. A gate trench (6), which penetrates the third layer (4) and the second layer (3) and reaches the first layer (2), is provided. A gate insulating film (8) covers the side wall of the gate trench (6). A gate electrode (9) is embedded in the gate trench (6) with the gate insulating film (8) therebetween. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2015026723-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9680006-B2 |
| priorityDate |
2011-09-26^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |