http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2016000342-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a62555ff12316a9a118542896b4c0af7 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28506 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K59-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K2102-3026 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28158 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1262 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1288 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-127 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1274 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78678 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66765 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28008 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4908 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-77 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12 |
| filingDate | 2014-10-01^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9e2659240916593c14a8094cec47527d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d1c6d11611be0501265668f9705310fc http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4019aa6fa7736b1e4e70be9fbf049d58 |
| publicationDate | 2016-01-07^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-2016000342-A1 |
| titleOfInvention | Array substrate, manufacturing method therefor, and display apparatus |
| abstract | An array substrate, a manufacturing method therefor, and a display apparatus. Patterns comprising a gate (100), a gate insulation layer (101) and a polysilicon active layer (102) are formed on a base substrate (10) by using a one-time patterning process. A passivation layer (103) is formed on the surface of the substrate on which the above patterns are formed, and patterns of a first via hole (104) and a second via hole (105) are formed on the surface of the passivation layer by using the one-time patterning process. Patterns of a source (106), a drain (107) and a pixel electrode (108) are formed by using the one-time patterning process on the surface of the substrate on which the above patterns are formed, wherein the source (106) is electrically connected to the polysilicon active layer (102) through the first via hole (104), and the drain (107) is electrically connected to the polysilicon active layer (102) through the second via hole (105). Patterns of a pixel defined layer (109) are formed by using the one-time patterning process on the surface of the substrate on which the above patterns are formed. The method reduces the number of times of using a mask exposure process in manufacturing the low-temperature polysilicon AMOLED array substrate. |
| priorityDate | 2014-06-30^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
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