http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2017011425-A1

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filingDate 2016-07-12^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7b00d2cbe5ecbfc704bced39e838c2e3
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publicationDate 2017-01-19^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber WO-2017011425-A1
titleOfInvention Vertical jfet and method of manufacturing the same
abstract A vertical JFET made by a process using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A maskless self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. The channel is doped via angled implantation, and the width of the trenches and mesas in the active cell region may optionally be varied from those in the termination region.
priorityDate 2015-07-14^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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