| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b6caea61bfde8a45e01a8deabff80d97 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-35
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-27 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5283
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76843
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53266
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76877
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-27
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-35 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11582
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-1157 |
| filingDate |
2017-05-25^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c02572981ba2bfb0272532e9bee3d429
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_290e5c351ffd823d99aa7d8864d3c6fd
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b2442f78fc9835ecdbe086c06c1676c8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f6783d763a9672ca504f7eabd16f56f0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_acee2aedae65067a83d2fc1bac774d00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b2299a025a2aed6b0c65d5bff46b62bc |
| publicationDate |
2018-02-15^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2018031094-A1 |
| titleOfInvention |
Three-dimensional memory device containing a lateral source contact and method of making the same |
| abstract |
A sacrificial film and an alternating stack of insulating layers and sacrificial material layers are sequentially formed over a substrate. A memory stack structure including a memory film and a vertical semiconductor channel is formed through the alternating stack and the sacrificial film on the substrate. A source level cavity is formed by introducing an etchant or a reactant through a backside trench and removing the sacrificial film. After removal of an annular portion of the memory film, a portion of the vertical semiconductor channel is converted into an annular source region by introducing electrical dopants into the channel. A source contact layer is formed in the source level cavity and directly on the annular source region. The sacrificial material layers are replaced with electrically conductive layers. The annular source region and the source contact layer can provide low source contact resistance in a three-dimensional NAND memory device. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11552091-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2021262236-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-109716521-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11521984-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11374020-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2021242328-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11282857-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11508748-B2 |
| priorityDate |
2016-08-12^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |