| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_7542cdde926ccc0ad7b27ea92c083088 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-467
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-621
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-452
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0804
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-1052
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-1016 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-128
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-467
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F21-71
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0806
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F21-53
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F21-74
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-1441 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-46 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F21-71 |
| filingDate |
2018-04-26^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a758aa3d7680d7aef413cb96c342ebb7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_456ec193d9ade387009f865c476a8baf
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e2c6832013e8b41e7a0439db70458116
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_188bb4d8bbb43f4fac0867512822dcd3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_baa04adc71cecd93fea4296afecf0068
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e380b26490e066f7ea19fb6cc84c659d |
| publicationDate |
2018-11-29^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2018217392-A1 |
| titleOfInvention |
Compute node security |
| abstract |
In various examples a compute node is described. The compute node has a central processing unit which implements a hardware transactional memory using at least one cache of the central processing unit. The compute node has a memory in communication with the central processing unit, the memory storing information comprising at least one of: code and data. The compute node has a processor which loads at least part of the information, from the memory into the cache. The processor executes transactions using the hardware transactional memory and at least the loaded information, such that the processor ensures that the loaded information remains in the cache until completion of the execution. |
| priorityDate |
2017-05-26^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |