| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ca748d5cbfb6d9d2f2c6013230fccd73 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-665
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66515 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-35
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42344 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-1157
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11573 |
| filingDate |
2018-07-13^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e794f7275293caa59206ad7fc60d76a1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4ce65f0f2d27ec3db4f9cb35e3b53ca0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ac6b01e22a0a0eaa4f658d22120fd101
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_84ce77bad130cf1a5ac2ffe05d2daad8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a5b63f4303ec3c09d5ca0d4f86324abc
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f94146fb646d496c5b13ab97aed8d042 |
| publicationDate |
2019-01-24^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2019018231-A1 |
| titleOfInvention |
INTEGRATED NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME |
| abstract |
The present invention provides systems and methods for forming a memory gate stack (MG) in a first region, and forming a sacrificial polysilicon gate on a high dielectric constant dielectric in a second region, the first and second regions. regions lying in a single substrate. Then, a selection gate (SG) may be formed adjacent to the MG stack in the first region of the semiconductor substrate. The sacrificial polysilicon gate may be replaced by a metal gate so as to form a logical field effect transistor (FET) in the second region. The substrate surfaces in the first and second regions are substantially coplanar. |
| priorityDate |
2017-07-19^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |