| abstract |
Methods, systems, and devices for canceling lock offsets in memory devices are disclosed. A memory device may include a sensing component including first and second transistors. In some cases, a memory device may further include a first capacitor coupled to the first transistor and a second capacitor coupled to the second transistor and a first switching component coupled between a voltage source and the first capacitor and the second capacitor. For example, the first switching component can be activated, a reference voltage can be applied to the detection component, and the first switching component can then be deactivated. In some examples, a voltage offset can be measured across the first and second capacitors. |