| abstract |
A clock generation circuit is disclosed. The clock generation circuit includes a logic gate configured to, in response to a control input receiving a first control signal, generate an output clock based on a first input clock received by a first identified clock input. The logic gate is further configured to, in response to the control input receiving the second control signal, generate the output clock based on a fixed logic level. The logic gate is further configured to, in response to the control input receiving the second control signal, generate the output clock based on the second input clock. |