| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c3a2f00e72ba6e4c09b6da573427fbed |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-35
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-27 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-27
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-27 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11582
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11521
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11556
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11568
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11573
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11526 |
| filingDate |
2022-02-17^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_199477384251dab3b895cd8a4f1babab
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ecf0b46470c49cf65fcf30b36723982d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_55da7bc364b9979de780c2f288d7000d |
| publicationDate |
2022-10-13^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2022216369-A1 |
| titleOfInvention |
Integrated assemblies and methods of forming integrated assemblies |
| abstract |
Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and said other region, and separates a first memory-block- region from a second memory-block-region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. Rings laterally surround lower regions of the conductive posts. The rings are between the conductive posts and the doped- semiconductor- material. The rings include laminates of two or more materials, with at least one of said two or more materials being insulative. Some embodiments include methods for forming integrated assemblies. |
| priorityDate |
2021-04-06^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |