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2020 – today
- 2020
[j8]Paolo Madoglio
, Yorgos Palaskas, Jörn Angel, Jakob M. Tomasik, Sven Hampel, Petra Schubert, Peter Preyler, Thomas Mayer, Thomas Bauernfeind, Peter Plechinger, Ashoke Ravi, Ofir Degani, Rotem Banin, Eshel Gordon, Dimo Martev, Timo Gossmann, Andreas Holm, Zdravko Boos:
A Cellular Multiband DTC-Based Digital Polar Transmitter With -153-dBc/Hz Noise in 14-nm FinFET. IEEE J. Solid State Circuits 55(7): 1830-1841 (2020)- [c8]Parmoon Seddighrad, Yorgos Palaskas, Hongtao Xu, Paolo Madoglio, Kailash Chandrashekar, David J. Allstot:
Transformer-Combining Digital PA with Efficiency Peaking at 0, -6, and -12 dB Backoff in 32nm CMOS. ISCAS 2020: 1-4
2010 – 2019
- 2019
- [c7]Yorgos Palaskas, Peter Plechinger, Ashoke Ravi, Ofir Degani, Rotem Banin, Eshel Gordon, Zdravko Boos, Paolo Madoglio, Jörn Angel, Jakob M. Tomasik, Sven Hampel, Petra Schubert, Peter Preyler, Thomas Mayer, Thomas Bauernfeind:
A Cellular Multiband DTC-Based Digital Polar Transmitter With -153 dBc/Hz Noise in 14-nm FinFET. ESSCIRC 2019: 179-182 - 2017
- [c6]Paolo Madoglio, Hongtao Xu, Kailash Chandrashekar, Luis Cuellar, Muhammad Faisal, Yee William Li, Hyung Seok Kim, Khoa Minh Nguyen, Yulin Tan, Brent R. Carlton, Vaibhav A. Vaidya, Yanjie Wang, Thomas Tetzlaff, Satoshi Suzuki, Amr Fahim, Parmoon Seddighrad, Jianyong Xie, Zhichao Zhang, Divya Shree Vemparala, Ashoke Ravi, Stefano Pellerano, Yorgos Palaskas:
13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications. ISSCC 2017: 226-227 - 2013
- [j7]Hyung Seok Kim, Carlos Ornelas, Kailash Chandrashekar, Dan Shi, Pin-en Su, Paolo Madoglio, Yee William Li, Ashoke Ravi:
A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique. IEEE J. Solid State Circuits 48(7): 1721-1729 (2013) - 2012
- [j6]Ashoke Ravi, Paolo Madoglio, Hongtao Xu, Kailash Chandrashekar, Marian Verhelst, Stefano Pellerano, Luis Cuellar, Mariano Aguirre-Hernandez, Masoud Sajadieh, J. E. Zarate-Roldan, Ofir Bochobza-Degani, Hasnain Lakdawala, Yorgos Palaskas:
A 2.4-GHz 20-40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS. IEEE J. Solid State Circuits 47(12): 3184-3196 (2012) - [c5]Hyung Seok Kim, Carlos Ornelas, Kailash Chandrashekar, Pin-en Su, Paolo Madoglio, Yee William Li, Ashoke Ravi:
A digital fractional-N PLL with a 3mW 0.004mm2 6-bit PVT and mismatch insensitive TDC. ESSCIRC 2012: 193-196 - [c4]Paolo Madoglio, Ashoke Ravi, Hongtao Xu, Kailash Chandrashekar, Marian Verhelst, Stefano Pellerano, Luis Cuellar, Mariano Aguirre, Masoud Sajadieh, Ofir B. Degani, Hasnain Lakdawala, Yorgos Palaskas:
A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS. ISSCC 2012: 168-170 - [c3]Kailash Chandrashekar, Stefano Pellerano, Paolo Madoglio, Ashoke Ravi, Yorgos Palaskas:
A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management. ISSCC 2012: 352-354 - 2010
- [j5]Salvatore Levantino, Marco Zanuso, Paolo Madoglio, Davide Tasca, Carlo Samori, Andrea L. Lacaita:
AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic. EURASIP J. Embed. Syst. 2010 (2010) - [j4]Paolo Madoglio, Ashoke Ravi, Luis Cuellar, Stefano Pellerano, Parmoon Seddighrad, Ismael Lomeli, Yorgos Palaskas:
A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving. IEEE J. Solid State Circuits 45(7): 1410-1420 (2010) - [j3]Marco Zanuso, Paolo Madoglio, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita:
Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(3): 548-555 (2010)
2000 – 2009
- 2009
- [j2]Stefano Pellerano, Paolo Madoglio, Yorgos Palaskas:
A 4.75-GHz Fractional Frequency Divider-by-1.25 With TDC-Based All-Digital Spur Calibration in 45-nm CMOS. IEEE J. Solid State Circuits 44(12): 3422-3433 (2009) - [c2]Paolo Madoglio, Ashoke Ravi, Luis Cuellar, Stefano Pellerano, Parmoon Seddighrad, Ismael Lomeli, Yorgos Palaskas:
A 2.5GHz, 6.9mW ΔΣ modulator with standard cell design in 45nm-LP CMOS using time-interleaving. ESSCIRC 2009: 152-155 - [c1]Stefano Pellerano, Paolo Madoglio, Yorgos Palaskas:
A 4.75GHz fractional frequency divider with digital spur calibration in 45nm CMOS. ISSCC 2009: 226-227 - 2007
- [j1]Paolo Madoglio, Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita:
Quantization Effects in All-Digital Phase-Locked Loops. IEEE Trans. Circuits Syst. II Express Briefs 54-II(12): 1120-1124 (2007)
Coauthor Index
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