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2020 – today
- 2024
[c38]Amy Whitcombe, Somnath Kundu, Hariprasad Chandrakumar, Abhishek Agrawal, Thomas William Brown, Steven Callender, Brent R. Carlton, Stefano Pellerano:
22.3 A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking. ISSCC 2024: 392-394- [c37]Sushil Subramanian, Todor Mladenov, Simon Schaal, Bishnu Patra, Lester Lampert, Nancy K. Robinson, Jeanette Roberts, Stefano Pellerano:
A Scalable mK Cryo-CMOS Demultiplexer Chip for Voltage Biasing and High-Speed Control of Silicon Qubit Gates. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j22]Amy Whitcombe
, Chun C. Lee, Asma Kuriparambil Thekkumpate, Somnath Kundu, Jaykant Timbadiya, Abhishek Agrawal, Brent R. Carlton, Peter Sagazio, Stefano Pellerano, Christopher D. Hull:
A VTC/TDC-Assisted 4× Interleaved 3.8 GS/s 7b 6.0 mW SAR ADC With 13 GHz ERBW. IEEE J. Solid State Circuits 58(4): 972-982 (2023) - [j21]Abhishek Agrawal, Amy Whitcombe, Woorim Shin, Ritesh Bhat, Somnath Kundu, Peter Sagazio, Hariprasad Chandrakumar, Thomas William Brown, Brent R. Carlton, Christopher Dennis Hull, Steven Callender, Stefano Pellerano:
A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET. IEEE J. Solid State Circuits 58(12): 3364-3379 (2023) - [c36]Abhishek Agrawal, Amy Whitcombe, Woorim Shin, Ritesh Bhat, Somnath Kundu, Peter Sagazio, Hariprasad Chandrakumar, Thomas William Brown, Brent R. Carlton, Christopher D. Hull, Steven Callender, Stefano Pellerano:
A 128Gb/s 1.95pJ/b D-Band Receiver with Integrated PLL and ADC in 22nm FinFET. ISSCC 2023: 284-285 - 2022
- [j20]Steven Callender, Abhishek Agrawal, Amy Whitcombe, Ritesh Bhat, Mustafijur Rahman, Chun C. Lee, Peter Sagazio, Georgios C. Dogiamis, Brent R. Carlton, Christopher D. Hull, Stefano Pellerano:
A Fully Integrated 160-Gb/s D-Band Transmitter Achieving 1.1-pJ/b Efficiency in 22-nm FinFET. IEEE J. Solid State Circuits 57(12): 3582-3598 (2022) - [c35]Stefano Pellerano, Sushil Subramanian, Jong Seok Park, Bishnu Patra, Todor Mladenov, Xiao Xue, Lieven M. K. Vandersypen, Masoud Babaie, Edoardo Charbon, Fabio Sebastiano:
Cryogenic CMOS for Qubit Control and Readout. CICC 2022: 1-8 - [c34]Vida Ilderem, Stefano Pellerano, Jim Tschanz, Tanay Karnik, Vivek De:
Innovations for Intelligent Edge. ESSCIRC 2022: 41-44 - [c33]Steven Callender, Amy Whitcombe, Abhishek Agrawal, Ritesh Bhat, Mustafijur Rahman, Chun C. Lee, Peter Sagazio, Georgios C. Dogiamis, Brent R. Carlton, Mark Chakravorti, Stefano Pellerano, Christopher D. Hull:
A Fully Integrated 160Gb/s D-Band Transmitter with 1.1 pJ/b Efficiency in 22nm FinFET Technology. ISSCC 2022: 78-80 - [c32]Somnath Kundu, Timo Huusari, Hao Luo, Abhishek Agrawal, Eduardo Alban, Sarah Shahraini, Thao Xiong, Dan Lake, Stefano Pellerano, Jason Mix, Nasser A. Kurd, Mohamed Abdel-moneum, Brent R. Carlton:
A 2-to-2.48GHz Voltage-Interpolator-Based Fractional-N Type-I Sampling PLL in 22nm FinFET Assisting Fast Crystal Startup. ISSCC 2022: 144-146 - [c31]Amy Whitcombe, Chun C. Lee, Asma Kuriparambil Thekkumpate, Somnath Kundu, Jaykant Timbadiya, Abhishek Agrawal, Brent R. Carlton, Peter Sagazio, Stefano Pellerano, Christopher D. Hull:
A 6.0mW 3.8GS/s 7b VTC/TDC-Assisted Interleaved SAR ADC with 13GHz ERBW. VLSI Technology and Circuits 2022: 170-171 - 2021
- [j19]Somnath Kundu, Likai Chai, Kailash Chandrashekar, Stefano Pellerano, Brent R. Carlton:
A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-N MDLL in 22-nm FinFET CMOS. IEEE J. Solid State Circuits 56(1): 43-54 (2021) - [j18]Kun-Da Chu, Steven Callender, Yanjie Wang, Jacques Christophe Rudell, Stefano Pellerano, Christopher D. Hull:
A Reconfigurable Non-Uniform Power-Combining V-Band PA With +17.9 dBm Psat and 26.5% PAE in 16-nm FinFET CMOS. IEEE J. Solid State Circuits 56(5): 1502-1513 (2021) - [j17]Jongseok Park, Sushil Subramanian, Lester Lampert, Todor Mladenov, Ilya Klotchkov, Dileep Kurian, Esdras Juarez Hernandez, Brando Perez Esparza, Sirisha Rani Kale, K. T. Asma Beevi, Shavindra P. Premaratne, Thomas Watson, Satoshi Suzuki, Mustafijur Rahman, Jaykant Timbadiya, Saksham Soni, Stefano Pellerano:
A Fully Integrated Cryo-CMOS SoC for State Manipulation, Readout, and High-Speed Gate Pulsing of Spin Qubits. IEEE J. Solid State Circuits 56(11): 3289-3306 (2021) - [c30]Jong Seok Park, Sushil Subramanian, Lester Lampert, Todor Mladenov, Ilya Klotchkov, Dileep Kurian, Esdras Juárez-Hernández, Brando Perez Esparza, Sirisha Rani Kale, K. T. Asma Beevi, Shavindra P. Premaratne, Thomas Watson, Satoshi Suzuki, Mustafijur Rahman, Jaykant Timbadiya, Saksham Soni, Stefano Pellerano:
A Fully Integrated Cryo-CMOS SoC for Qubit Control in Quantum Computers Capable of State Manipulation, Readout and High-Speed Gate Pulsing of Spin Qubits in Intel 22nm FFL FinFET Technology. ISSCC 2021: 208-210 - 2020
- [j16]Jeroen Petrus Gerardus van Dijk, Bishnu Patra, Sushil Subramanian, Xiao Xue, Nodar Samkharadze, Andrea Corna, Charles Jeon, Farhana Sheikh, Esdras Juarez Hernandez, Brando Perez Esparza, Huzaifa Rampurawala, Brent R. Carlton, Surej Ravikumar, Carlos Nieva, Sungwon Kim, Hyung-Jin Lee, Amir Sammak, Giordano Scappucci, Menno Veldhorst, Lieven M. K. Vandersypen, Edoardo Charbon, Stefano Pellerano, Masoud Babaie, Fabio Sebastiano:
A Scalable Cryo-CMOS Controller for the Wideband Frequency-Multiplexed Control of Spin Qubits and Transmons. IEEE J. Solid State Circuits 55(11): 2930-2946 (2020) - [j15]Jeroen P. G. van Dijk, Bishnu Patra, Stefano Pellerano, Edoardo Charbon, Fabio Sebastiano, Masoud Babaie:
Designing a DDS-Based SoC for High-Fidelity Multi-Qubit Control. IEEE Trans. Circuits Syst. 67-I(12): 5380-5393 (2020) - [c29]Somnath Kundu, Likai Chai, Kailash Chandrashekar, Stefano Pellerano, Brent R. Carlton:
25.5 A Self-Calibrated 1.2-to-3.8GHz 0.0052mm2 Synthesized Fractional-N MDLL Using a 2b Time-Period Comparator in 22nm FinFET CMOS. ISSCC 2020: 276-278 - [c28]Bishnu Patra, Jeroen P. G. van Dijk, Sushil Subramanian, Andrea Corna, Xiao Xue, Charles Jeon, Farhana Sheikh, Esdras Juarez Hernandez, Brando Perez Esparza, Huzaifa Rampurawala, Brent R. Carlton, Nodar Samkharadze, Surej Ravikumar, Carlos Nieva, Sungwon Kim, Hyung-Jin Lee, Amir Sammak, Giordano Scappucci, Menno Veldhorst, Lieven M. K. Vandersypen, Masoud Babaie, Fabio Sebastiano, Edoardo Charbon, Stefano Pellerano:
19.1 A Scalable Cryo-CMOS 2-to-20GHz Digitally Intensive Controller for 4×32 Frequency Multiplexed Spin Qubits/Transmons in 22nm FinFET Technology for Quantum Computers. ISSCC 2020: 304-306
2010 – 2019
- 2019
- [j14]Steven Callender, Stefano Pellerano, Christopher D. Hull:
An $E$ -Band Power Amplifier With 26.3% PAE and 24-GHz Bandwidth in 22-nm FinFET CMOS. IEEE J. Solid State Circuits 54(5): 1266-1273 (2019) - [c27]Stefano Pellerano, Steven Callender, Woorim Shin, Yanjie Wang, Somnath Kundu, Abhishek Agrawal, Peter Sagazio, Brent R. Carlton, Farhana Sheikh, Arnaud Amadjikpe, William J. Lambert, Divya Shree Vemparala, Mark Chakravorti, Satoshi Suzuki, Robert Flory, Chris Hull:
A Scalable 71-to-76GHz 64-Element Phased-Array Transceiver Module with 2×2 Direct-Conversion IC in 22nm FinFET CMOS Technology. ISSCC 2019: 174-176 - 2018
- [j13]Peter Sagazio, Steven Callender, Woorim Shin, Oner Orhan, Stefano Pellerano, Christopher D. Hull:
Architecture and Circuit Choices for 5G Millimeter-Wave Beamforming Transceivers. IEEE Commun. Mag. 56(12): 186-192 (2018) - [j12]Jong Seok Park, Yanjie Wang, Stefano Pellerano, Christopher D. Hull, Hua Wang:
A CMOS Wideband Current-Mode Digital Polar Power Amplifier With Built-In AM-PM Distortion Self-Compensation. IEEE J. Solid State Circuits 53(2): 340-356 (2018) - [j11]Erkan Alpman, Ahmad Khairi, Richard Dorrance, Minyoung Park, V. Srinivasa Somayazulu, Jeffrey R. Foerster, Ashoke Ravi, Jeyanandh Paramesh, Stefano Pellerano:
802.11g/n Compliant Fully Integrated Wake-Up Receiver With -72-dBm Sensitivity in 14-nm FinFET CMOS. IEEE J. Solid State Circuits 53(5): 1411-1422 (2018) - [c26]Steven Callender, Woorim Shin, Hyung-Jin Lee, Stefano Pellerano, Christopher D. Hull:
FinFET for mm Wave - Technology and Circuit Design Challenges. BCICTS 2018: 168-173 - [c25]Chun-Huat Heng, David McLaurin, Stefano Pellerano:
Session 4 overview: mm-Wave radios for 5G and beyond: Wireless subcommittee. ISSCC 2018: 64-65 - [c24]Alan Wong, Xin He, Stefano Pellerano:
Session 9 overview: Wireless transceivers and techniques: Wireless subcommittee. ISSCC 2018: 156-157 - [c23]Howard C. Luong, Kyoo Hyun Lim, Stefano Pellerano:
Session 28 overview: Wireless connectivity: Wireless subcommittee. ISSCC 2018: 440-441 - 2017
- [c22]Paolo Madoglio, Hongtao Xu, Kailash Chandrashekar, Luis Cuellar, Muhammad Faisal, Yee William Li, Hyung Seok Kim, Khoa Minh Nguyen, Yulin Tan, Brent R. Carlton, Vaibhav A. Vaidya, Yanjie Wang, Thomas Tetzlaff, Satoshi Suzuki, Amr Fahim, Parmoon Seddighrad, Jianyong Xie, Zhichao Zhang, Divya Shree Vemparala, Ashoke Ravi, Stefano Pellerano, Yorgos Palaskas:
13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications. ISSCC 2017: 226-227 - [c21]Jong Seok Park, Yanjie Wang, Stefano Pellerano, Christopher D. Hull, Hua Wang:
13.8 A 24dBm 2-to-4.3GHz wideband digital Power Amplifier with built-in AM-PM distortion self-compensation. ISSCC 2017: 230-231 - [c20]Stefano Pellerano, Sungdae Choi, Jan M. Rabaey:
EE2: Intelligent machines: Will the technological singularity happen? ISSCC 2017: 521 - 2016
- [c19]Stefano Pellerano, Ahmad Mirzaei, Chih-Ming Hung, Jan Craninckx, Kenichi Okada, Vojkan Vidojkovic:
F3: Radio architectures and circuits towards 5G. ISSCC 2016: 498-501 - 2015
- [c18]Piet Wambacq, Stefano Pellerano, Sven Mattisson, Shouhei Kousai, Ali Afsahi, Taizo Yamawaki:
F5: Advanced RF CMOS transmitter techniques. ISSCC 2015: 1-2 - [c17]Stefano Pellerano, Koji Takinami:
Session 19 overview: Advanced wireless techniques: Wireless subcommittee. ISSCC 2015: 340-341 - [c16]Vamsi Talla, Stefano Pellerano, Hongtao Xu, Ashoke Ravi, Yorgos Palaskas:
Wi-Fi RF energy harvesting for battery-free wearable radio platforms. IEEE RFID 2015: 47-54 - 2013
- [j10]Hasnain Lakdawala, Mark Schaecher, Chang-Tsung Fu, Rahul Dilip Limaye, Jon Duster, Yulin Tan, Ajay Balankutty, Erkan Alpman, Chun C. Lee, Khoa Minh Nguyen, Hyung-Jin Lee, Ashoke Ravi, Satoshi Suzuki, Brent R. Carlton, Hyung Seok Kim, Marian Verhelst, Stefano Pellerano, Tong Kim, Satish Venkatesan, Durgesh Srivastava, Peter Vandervoorn, Jad Rizk, Chia-Hong Jan, Sunder Ramamurthy, Raj Yavatkar, Krishnamurthy Soumyanath:
A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver. IEEE J. Solid State Circuits 48(1): 91-103 (2013) - 2012
- [j9]Ashoke Ravi, Paolo Madoglio, Hongtao Xu, Kailash Chandrashekar, Marian Verhelst, Stefano Pellerano, Luis Cuellar, Mariano Aguirre-Hernandez, Masoud Sajadieh, J. E. Zarate-Roldan, Ofir Bochobza-Degani, Hasnain Lakdawala, Yorgos Palaskas:
A 2.4-GHz 20-40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS. IEEE J. Solid State Circuits 47(12): 3184-3196 (2012) - [c15]Hasnain Lakdawala, Mark Schaecher, Chang-Tsung Fu, Rahul Dilip Limaye, Jon Duster, Yulin Tan, Ajay Balankutty, Erkan Alpman, Chun C. Lee, Satoshi Suzuki, Brent R. Carlton, Hyung Seok Kim, Marian Verhelst, Stefano Pellerano, Tong Kim, Durgesh Srivastava, Satish Venkatesan, Hyung-Jin Lee, Peter Vandervoorn, Jad Rizk, Chia-Hong Jan, Krishnamurthy Soumyanath, Sunder Ramamurthy:
32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver. ISSCC 2012: 62-64 - [c14]Paolo Madoglio, Ashoke Ravi, Hongtao Xu, Kailash Chandrashekar, Marian Verhelst, Stefano Pellerano, Luis Cuellar, Mariano Aguirre, Masoud Sajadieh, Ofir B. Degani, Hasnain Lakdawala, Yorgos Palaskas:
A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS. ISSCC 2012: 168-170 - [c13]Kailash Chandrashekar, Stefano Pellerano, Paolo Madoglio, Ashoke Ravi, Yorgos Palaskas:
A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management. ISSCC 2012: 352-354 - [c12]Yulin Tan, Jon Duster, Chang-Tsung Fu, Erkan Alpman, Ajay Balankutty, Chun C. Lee, Ashoke Ravi, Stefano Pellerano, Kailash Chandrashekar, Hyung Seok Kim, Brent R. Carlton, Satoshi Suzuki, M. Shafi, Yorgos Palaskas, Hasnain Lakdawala:
A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS. VLSIC 2012: 76-77 - 2011
- [c11]Ajay Balankutty, Stefano Pellerano, Telesphor Kamgaing, Kranti Tantwai, Yorgos Palaskas:
A 12-element 60GHz CMOS phased array transmitter on LTCC package with integrated antennas. A-SSCC 2011: 273-276 - 2010
- [j8]Paolo Madoglio, Ashoke Ravi, Luis Cuellar, Stefano Pellerano, Parmoon Seddighrad, Ismael Lomeli, Yorgos Palaskas:
A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving. IEEE J. Solid State Circuits 45(7): 1410-1420 (2010) - [j7]Stefano Pellerano, Javier Alvarado Jr., Yorgos Palaskas:
A mm-Wave Power-Harvesting RFID Tag in 90 nm CMOS. IEEE J. Solid State Circuits 45(8): 1627-1637 (2010)
2000 – 2009
- 2009
- [j6]Stefano Pellerano, Paolo Madoglio, Yorgos Palaskas:
A 4.75-GHz Fractional Frequency Divider-by-1.25 With TDC-Based All-Digital Spur Calibration in 45-nm CMOS. IEEE J. Solid State Circuits 44(12): 3422-3433 (2009) - [c10]Stefano Pellerano, Javier Alvarado Jr., Yorgos Palaskas:
A mm-wave power harvesting RFID tag in 90nm CMOS. CICC 2009: 677-680 - [c9]Paolo Madoglio, Ashoke Ravi, Luis Cuellar, Stefano Pellerano, Parmoon Seddighrad, Ismael Lomeli, Yorgos Palaskas:
A 2.5GHz, 6.9mW ΔΣ modulator with standard cell design in 45nm-LP CMOS using time-interleaving. ESSCIRC 2009: 152-155 - [c8]Stefano Pellerano, Paolo Madoglio, Yorgos Palaskas:
A 4.75GHz fractional frequency divider with digital spur calibration in 45nm CMOS. ISSCC 2009: 226-227 - 2008
- [j5]Stefano Pellerano, Yorgos Palaskas, Krishnamurthy Soumyanath:
A 64 GHz LNA With 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS. IEEE J. Solid State Circuits 43(7): 1542-1552 (2008) - [c7]Yorgos Palaskas, Ashoke Ravi, Stefano Pellerano:
MIMO techniques for high data rate radio communications. CICC 2008: 141-148 - [c6]Hiroyuki Ito, Hasnain Lakdawala, Ashoke Ravi, Stefano Pellerano, Rick Ruby, Krishnamurthy Soumyanath, Kazuya Masu:
A 1.7-GHz 1.5-mW digitally-controlled FBAR oscillator with 0.03-ppb resolution. ESSCIRC 2008: 98-101 - [c5]Stefano Pellerano, Rajarshi Mukhopadhyay, Ashoke Ravi, Joy Laskar, Yorgos Palaskas:
A 39.1-to-41.6GHz ΔΣ Fractional-N Frequency Synthesizer in 90nm CMOS. ISSCC 2008: 484-485 - 2007
- [c4]Stefano Pellerano, Yorgos Palaskas, Krishnamurthy Soumyanath:
A 64GHz 6.5 dB NF 15.5 dB gain LNA in 90nm CMOS. ESSCIRC 2007: 352-355 - 2006
- [j4]Yorgos Palaskas, Stewart S. Taylor, Stefano Pellerano, Ian A. Rippke, Ralph E. Bishop, Ashoke Ravi, Hasnain Lakdawala, Krishnamurthy Soumyanath:
A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process. IEEE J. Solid State Circuits 41(8): 1757-1763 (2006) - [j3]Yorgos Palaskas, Ashoke Ravi, Stefano Pellerano, Brent R. Carlton, Mostafa A. Elmala, Ralph E. Bishop, Gaurab Banerjee, Rich B. Nicholls, Stanley K. Ling, Nati Dinur, Stewart S. Taylor, Krishnamurthy Soumyanath:
A 5-GHz 108-Mb/s 2 $\times$2 MIMO Transceiver RFIC With Fully Integrated 20.5-dBm ${\rm P}_{\rm 1dB}$ Power Amplifiers in 90-nm CMOS. IEEE J. Solid State Circuits 41(12): 2746-2756 (2006) - [c3]Yorgos Palaskas, Ashoke Ravi, Stefano Pellerano, Brent R. Carlton, Mostafa A. Elmala, Ralph E. Bishop, Gaurab Banerjee, Rich B. Nicholls, Stanley K. Ling, Stewart S. Taylor, Krishnamurthy Soumyanath:
A 5GHz 108Mb/s 2x2 MIMO Transceiver with Fully Integrated +16dBm PAs in 90nm CMOS. ISSCC 2006: 1420-1429 - 2005
- [c2]Yorgos Palaskas, Stewart S. Taylor, Stefano Pellerano, Ian A. Rippke, Ralph E. Bishop, Ashoke Ravi, Hasnain Lakdawala, Krishnamurthy Soumyanath:
A 5 GHz class-AB power amplifier in 90 nm CMOS with digitally-assisted AM-PM correction. CICC 2005: 813-816 - 2004
- [b1]Stefano Pellerano:
Fully-integrated frequency synthesizers for multi-standard WLAN applications. Polytechnic University of Milan, Italy, 2004 - [j2]Stefano Pellerano, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita:
A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider. IEEE J. Solid State Circuits 39(2): 378-383 (2004) - [j1]Salvatore Levantino, Luca Romanò, Stefano Pellerano, Carlo Samori, Andrea L. Lacaita:
Phase noise in digital frequency dividers. IEEE J. Solid State Circuits 39(5): 775-784 (2004) - 2003
- [c1]Andrea Giovanni Bonfanti, Salvatore Levantino, Stefano Pellerano, Carlo Samori, Andrea L. Lacaita, Felice Torrisi:
A voltage-controlled oscillator for IEEE 802.11a and HiperLAN2 application. ESSCIRC 2003: 695-698
Coauthor Index
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