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ORCIDKazuyoshi Takagi
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2020 – today
- 2021
[j27]Mingyang Kou
, Pei-Yi Cheng, Jun Zeng, Tsung-Yi Ho, Kazuyoshi Takagi, Hailong Yao:
Splitter-Aware Multiterminal Routing With Length-Matching Constraint for RSFQ Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(11): 2251-2264 (2021)- 2020
- [j26]Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi:
mROS: A Lightweight Runtime Environment of ROS 1 nodes for Embedded Devices. J. Inf. Process. 28: 150-160 (2020)
2010 – 2019
- 2019
- [j25]Nobutaka Kito, Ryota Odaka, Kazuyoshi Takagi:
Rapid Single-Flux-Quantum Truncated Multiplier Based on Bit-Level Processing. IEICE Trans. Electron. 102-C(7): 607-611 (2019) - [j24]Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi:
Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses. IPSJ Trans. Syst. LSI Des. Methodol. 12: 78-80 (2019) - [c13]Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi:
mROS: A Lightweight Runtime Environment for Robot Software Components onto Embedded Devices. HEART 2019: 7:1-7:6 - 2018
- [j23]Kotaro Matsumoto, Kazuyoshi Takagi, Naofumi Takagi:
Algorithms for Evaluating the Matrix Polynomial I+A+A2+...+AN-1 with Reduced Number of Matrix Multiplications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(2): 467-471 (2018) - [c12]Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi:
Design concept of a lightweight runtime environment for robot software components onto embedded devices: work-in-progress. EMSOFT 2018: 6 - [c11]Pei-Yi Cheng, Kazuyoshi Takagi, Tsung-Yi Ho:
Multi-terminal routing with length-matching for rapid single flux quantum circuits. ICCAD 2018: 111 - 2016
- [j22]Guang-Ming Tang, Kazuyoshi Takagi, Naofumi Takagi:
RSFQ 4-bit Bit-Slice Integer Multiplier. IEICE Trans. Electron. 99-C(6): 697-702 (2016) - [j21]Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi:
High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation. IEICE Trans. Electron. 99-C(6): 703-709 (2016) - [c10]Hideki Takase, Kazumi Aono, Yutaka Matsubara, Kazuyoshi Takagi, Naofumi Takagi:
An evaluation framework of OS-level power managements for the big.LITTLE architecture. NEWCAS 2016: 1-4 - 2015
- [j20]Takahiro Kawaguchi, Kazuyoshi Takagi, Naofumi Takagi:
A Verification Method for Single-Flux-Quantum Circuits Using Delay-Based Time Frame Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2556-2564 (2015) - [j19]Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi:
An Allocation Optimization Method for Partially-reliable Scratch-pad Memory in Embedded Systems. Inf. Media Technol. 10(3): 420-424 (2015) - [j18]Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi:
An Allocation Optimization Method for Partially-reliable Scratch-pad Memory in Embedded Systems. IPSJ Trans. Syst. LSI Des. Methodol. 8: 100-104 (2015) - 2014
- [j17]Shuichi Nagasawa, Kenji Hinode, Tetsuro Satoh, Mutsuo Hidaka, Hiroyuki Akaike, Akira Fujimaki, Nobuyuki Yoshikawa, Kazuyoshi Takagi, Naofumi Takagi:
Nb 9-Layer Fabrication Process for Superconducting Large-Scale SFQ Circuits and Its Process Evaluation. IEICE Trans. Electron. 97-C(3): 132-140 (2014) - [j16]Kazuyoshi Takagi, Nobutaka Kito, Naofumi Takagi:
Circuit Description and Design Flow of Superconducting SFQ Logic Circuits. IEICE Trans. Electron. 97-C(3): 149-156 (2014) - [j15]Akira Fujimaki, Masamitsu Tanaka, Ryo Kasagi, Katsumi Takagi, Masakazu Okada, Yuhi Hayakawa, Kensuke Takata, Hiroyuki Akaike, Nobuyuki Yoshikawa, Shuichi Nagasawa, Kazuyoshi Takagi, Naofumi Takagi:
Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors. IEICE Trans. Electron. 97-C(3): 157-165 (2014) - [j14]Xizhu Peng, Yuki Yamanashi, Nobuyuki Yoshikawa, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi, Mutsuo Hidaka:
Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm2 Nb Process. IEICE Trans. Electron. 97-C(3): 188-193 (2014) - [j13]Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi:
Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2498-2506 (2014) - [c9]Kazumi Aono, Atsushi Iwata, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi:
An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Maximize the Operation Quality. HPCC/CSS/ICESS 2014: 546-549 - 2013
- [c8]Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi:
A Buffering Method for Parallelized Loop with Non-Uniform Dependencies in High-Level Synthesis. ICA3PP (1) 2013: 390-401 - 2012
- [j12]Kazuhiro Nakamura, Ryo Shimazaki, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi:
A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition. IEICE Trans. Electron. 95-C(4): 456-467 (2012) - [j11]Katsuki Kobayashi, Naofumi Takagi, Kazuyoshi Takagi:
Fast inversion algorithm in GF(2m) suitable for implementation with a polynomial multiply instruction on GF(2). IET Comput. Digit. Tech. 6(3): 180-185 (2012) - 2011
- [j10]Kazuyoshi Takagi, Yuki Ito, Shota Takeshima, Masamitsu Tanaka, Naofumi Takagi:
Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits. IEICE Trans. Electron. 94-C(3): 288-295 (2011) - 2010
- [j9]Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi:
A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing. IEICE Trans. Inf. Syst. 93-D(2): 300-305 (2010) - [j8]Masamitsu Tanaka, Koji Obata, Yuki Ito, Shota Takeshima, Motoki Sato, Kazuyoshi Takagi, Naofumi Takagi, Hiroyuki Akaike, Akira Fujimaki:
Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A* Algorithm. IEICE Trans. Electron. 93-C(4): 435-439 (2010)
2000 – 2009
- 2008
- [j7]Koji Obata, Kazuyoshi Takagi, Naofumi Takagi:
A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3772-3782 (2008) - [c7]Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi:
Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems. ISCAS 2008: 1688-1691 - 2007
- [j6]Koji Obata, Kazuyoshi Takagi, Naofumi Takagi:
Logic Synthesis Method for Dual-Rail RSFQ Digital Circuits Using Root-Shared Binary Decision Diagrams. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(1): 257-266 (2007) - [j5]Koji Obata, Kazuyoshi Takagi, Naofumi Takagi:
A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits. IEICE Trans. Electron. 90-C(12): 2278-2284 (2007) - [c6]Katsuki Kobayashi, Naofumi Takagi, Kazuyoshi Takagi:
An Algorithm for Inversion in GF(2^m) Suitable for Implementation Using a Polynomial Multiply Instruction on GF(2). IEEE Symposium on Computer Arithmetic 2007: 105-112 - [c5]Satoshi Komatsu, Kazuyoshi Takagi, Masahiro Fujita, Kunihiro Asada:
VLSI CAD Education and Exercise Course with Public Domain Tools. MSE 2007: 111-112 - 2006
- [j4]Naofumi Takagi, Shunsuke Kadowaki, Kazuyoshi Takagi:
A Hardware Algorithm for Integer Division Using the SD2 Representation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(10): 2874-2881 (2006) - [c4]Shigeru Yamashita, Katsunori Tanaka, Hideyuki Takada, Koji Obata, Kazuyoshi Takagi:
A transduction-based framework to synthesize RSFQ circuits. ASP-DAC 2006: 266-272 - 2005
- [c3]Naofumi Takagi, Shunsuke Kadowaki, Kazuyoshi Takagi:
A Hardware Algorithm for Integer Division. IEEE Symposium on Computer Arithmetic 2005: 140-146 - 2003
- [j3]Naofumi Takagi, Daisuke Matsuoka, Kazuyoshi Takagi:
Digit-Recurrence Algorithm for Computing Reciprocal Square-Root. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(1): 221-228 (2003) - 2002
- [j2]Yasuaki Watanabe, Naofumi Takagi, Kazuyoshi Takagi:
A VLSI Algorithm for Division in GF(2m) Based on Extended Binary GCD Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(5): 994-999 (2002) - 2001
- [j1]Naofumi Takagi, Jun-ichi Yoshiki, Kazuyoshi Takagi:
A Fast Algorithm for Multiplicative Inversion in GF(2m) Using Normal Basis. IEEE Trans. Computers 50(5): 394-398 (2001) - 2000
- [c2]Shinji Kimura, Hiroyuki Kida, Kazuyoshi Takagi, Tatsumori Abematsu, Katsumasa Watanabe:
An application specific Java processor with reconfigurabilities. ASP-DAC 2000: 25-26
1990 – 1999
- 1998
- [c1]Kazuhiro Nakamura, Kazuyoshi Takagi, Shinji Kimura, Katsumasa Watanabe:
Waiting false path analysis of sequential logic circuits for performance optimization. ICCAD 1998: 392-395
Coauthor Index
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