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2020 – today
- 2024
- [j130]Riccardo Della Sala, Francesco Centurelli, Giuseppe Scotti, Gaetano Palumbo:
Rail to Rail ICMR and High Performance ULV Standard-Cell-Based Comparator for Biomedical and IoT Applications. IEEE Access 12: 4642-4659 (2024) - 2023
- [j129]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
Very-Low-Voltage Charge Pump Topologies for IoT Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 70(6): 2283-2292 (2023) - [c159]Javier Beloso-Legarra, Antonio Lopez-Martin, Carlos Aristoteles De la Cruz, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
GBW Optimization in Two-Stage OTAs Operating in Weak Inversion. DCIS 2023: 1-4 - [c158]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
Fully On-Chip Charge Pump-based Boost Converter in 65-nm CMOS for Single Solar Cell Powered IC. ISCAS 2023: 1-5 - [c157]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
Triple Clock Boosted Voltage Multiplier: A Design Strategy to Heavily Reduce Rise Time. NEWCAS 2023: 1-5 - [c156]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
An Energy-Efficient Design Strategy for Dickson Charge Pumps with Linear Distributed Capacitance. NEWCAS 2023: 1-5 - 2022
- [j128]Hamed Aminzadeh, Alfio Dario Grasso, Gaetano Palumbo:
A Methodology to Derive a Symbolic Transfer Function for Multistage Amplifiers. IEEE Access 10: 14062-14075 (2022) - [j127]Federico Nicolas Guerrero, Enrique Mario Spinelli, Alfio Dario Grasso, Gaetano Palumbo:
Double-Differential Amplifier for sEMG Measurement by Means of a Current-Mode Approach. IEEE Access 10: 45870-45880 (2022) - [j126]Gianluca Giustolisi, Gaetano Palumbo:
Analysis and Comparison in the Energy-Delay Space of Nanometer CMOS One-Bit Full-Adders. IEEE Access 10: 75482-75494 (2022) - [j125]Gianluca Giustolisi, Rosario Mita, Gaetano Palumbo, Giuseppe Scotti:
A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers. IEEE Access 10: 99702-99708 (2022) - [j124]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo, Toru Tanzawa:
A Charge Loss Aware Advanced Model of Dickson Voltage Multipliers. IEEE Access 10: 118082-118092 (2022) - [j123]Alfio Dario Grasso, Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
Single miller capacitor frequency compensation techniques: Theoretical comparison and critical review. Int. J. Circuit Theory Appl. 50(5): 1462-1486 (2022) - [j122]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
The Dickson Charge Pump as a Signal Amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. 69(9): 3476-3489 (2022) - [j121]Javier Beloso-Legarra, Alfio Dario Grasso, Antonio J. López-Martín, Gaetano Palumbo, Salvatore Pennisi:
Two-Stage OTA With All Subthreshold MOSFETs and Optimum GBW to DC-Current Ratio. IEEE Trans. Circuits Syst. II Express Briefs 69(7): 3154-3158 (2022) - [j120]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
A Bulk Current Regulation Technique for Dual-Branch Cross-Coupled Charge Pumps. IEEE Trans. Circuits Syst. II Express Briefs 69(10): 4128-4132 (2022) - 2021
- [j119]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
A Memory-Targeted Dynamic Reconfigurable Charge Pump to Achieve a Power Consumption Reduction in IoT Nodes. IEEE Access 9: 41958-41964 (2021) - [j118]Gianluca Giustolisi, Gaetano Palumbo:
Design of CMOS three-stage amplifiers for near-to-minimum settling-time. Microelectron. J. 107: 104939 (2021) - [j117]Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo:
Design of Low-Voltage Power Efficient Frequency Dividers in Folded MOS Current Mode Logic. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 680-691 (2021) - [j116]Gianluca Giustolisi, Gaetano Palumbo:
Design of Three-Stage OTA Based on Settling-Time Requirements Including Large and Small Signal Behavior. IEEE Trans. Circuits Syst. I Regul. Pap. 68(3): 998-1011 (2021) - [j115]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo, Toru Tanzawa:
Charge Pumps for Ultra-Low-Power Applications: Analysis, Design, and New Solutions. IEEE Trans. Circuits Syst. II Express Briefs 68(8): 2895-2901 (2021) - [j114]Francesco Centurelli, Giuseppe Scotti, Gaetano Palumbo:
A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 29(5): 998-1008 (2021) - [c155]Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo:
A Low-Voltage High-Performance Frequency Divider exploiting Folded MCML. ISCAS 2021: 1-5 - [c154]Gianluca Giustolisi, Gaetano Palumbo:
Design of Three-Stage OTAs from Settling-Time and Slew-Rate Constraints. ISCAS 2021: 1-5 - [c153]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
Comparison of the Wide-Frequency Range Dynamic Behavior of the Dickson and Cockcroft-Walton Voltage Multipliers. MWSCAS 2021: 348-351 - [c152]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
Dickson Charge Pump: Design Strategy for Optimum Efficiency. NEWCAS 2021: 1-4 - 2020
- [j113]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
A Subthreshold Cross-Coupled Hybrid Charge Pump for 50-mV Cold-Start. IEEE Access 8: 188959-188969 (2020) - [j112]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
A simple and effective design strategy to increase power conversion efficiency of linear charge pumps. Int. J. Circuit Theory Appl. 48(2): 157-161 (2020) - [j111]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo, Toru Tanzawa:
Linear distribution of capacitance in Dickson charge pumps to reduce rise time. Int. J. Circuit Theory Appl. 48(4): 555-566 (2020) - [j110]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
Current-mode body-biased switch to increase performance of linear charge pumps. Int. J. Circuit Theory Appl. 48(11): 1864-1872 (2020) - [j109]Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo:
Delay models and design guidelines for MCML gates with resistor or PMOS load. Microelectron. J. 99: 104755 (2020) - [j108]Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo:
A Novel 0.5 V MCML D-Flip-Flop Topology Exploiting Forward Body Bias Threshold Lowering. IEEE Trans. Circuits Syst. II Express Briefs 67-II(3): 560-564 (2020) - [j107]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
A High-Performance Charge Pump Topology for Very-Low-Voltage Applications. IEEE Trans. Circuits Syst. II Express Briefs 67-II(7): 1304-1308 (2020) - [j106]Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo:
Charge Pump Improvement for Energy Harvesting Applications by Node Pre-Charging. IEEE Trans. Circuits Syst. 67-II(12): 3312-3316 (2020) - [j105]Gaetano Palumbo, Giuseppe Scotti:
A Multi-Folded MCML for Ultra-Low-Voltage High-Performance in Deeply Scaled CMOS. IEEE Trans. Circuits Syst. 67-I(12): 4696-4706 (2020)
2010 – 2019
- 2019
- [j104]Gianluca Giustolisi, Gaetano Palumbo, Salvatore Pennisi:
Class-AB CMOS output stages suitable for low-voltage amplifiers in nanometer technologies. Microelectron. J. 92 (2019) - [j103]Andrea Ballo, Alfio Dario Grasso, Gianluca Giustolisi, Gaetano Palumbo:
Optimized Charge Pump With Clock Booster for Reduced Rise Time or Silicon Area. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1977-1981 (2019) - [j102]Gianluca Giustolisi, Gaetano Palumbo:
In-Depth Analysis of Pole-Zero Compensations in CMOS Operational Transconductance Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(12): 4557-4570 (2019) - 2018
- [j101]Gianluca Giustolisi, Gaetano Palumbo:
Bessel-like compensation of three-stage operational transconductance amplifiers. Int. J. Circuit Theory Appl. 46(4): 729-747 (2018) - [j100]Giulia Di Capua, Nuno Horta, Francisco V. Fernández, Günhan Dündar, Salvatore Pennisi, Gaetano Palumbo, Massimo Alioto, Gianluca Giustolisi:
Guest Editorial Special Issue on Selected Papers from PRIME 2017 and SMACD 2017. Integr. 63: 273-274 (2018) - [j99]Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
Switched-Capacitor Power Management Integrated Circuit for Autonomous Internet of Things Node. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1455-1459 (2018) - [j98]Alfio Dario Grasso, Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
High-Performance Three-Stage Single-Miller CMOS OTA With No Upper Limit of CL. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1529-1533 (2018) - [j97]Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
Dual Push-Pull High-Speed Rail-to-Rail CMOS Buffer Amplifier for Flat-Panel Displays. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1879-1883 (2018) - [c151]Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo:
A Novel 0.6V MCML D-Latch Topology exploiting Dynamic Body Bias Threshold Lowering. ICECS 2018: 233-236 - [c150]Gianluca Giustolisi, Gaetano Palumbo:
Design of CMOS OTAs with Settling-Time Constraints. ICECS 2018: 505-508 - [c149]Andrea Ballo, Gianluca Giustolisi, Alfio Dario Grasso, Gaetano Palumbo:
A Clock Boosted Charge Pump with Reduced Rise Time. ICECS 2018: 605-608 - [c148]Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi, Davide Marano:
Three-stage single-miller CMOS OTA driving 10 nF with 1.46-MHz GBW. ICICDT 2018: 37-40 - [c147]Gianluca Giustolisi, Gaetano Palumbo:
Non-Inverting Class-AB CMOS Output Stage for Driving High-Capacitive Loads. ISCAS 2018: 1-4 - [c146]Gianluca Giustolisi, Gaetano Palumbo:
Settling-time oriented OTA design through the approximation of the ideal delay. ISCAS 2018: 1-4 - [c145]Davide Bellizia, Gaetano Palumbo, Giuseppe Scotti, Alessandro Trifiletti:
A Novel Very Low Voltage Topology to implement MCML XOR Gates. PRIME 2018: 157-160 - 2017
- [j96]Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi, Willy Sansen:
The noise performance of CMOS Miller operational transconductance amplifiers with embedded current-buffer frequency compensation. Int. J. Circuit Theory Appl. 45(4): 457-465 (2017) - [j95]Gianluca Giustolisi, Gaetano Palumbo:
Robust design of CMOS amplifiers oriented to settling-time specification. Int. J. Circuit Theory Appl. 45(10): 1329-1348 (2017) - [j94]Giuseppe Scotti, Davide Bellizia, Alessandro Trifiletti, Gaetano Palumbo:
Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3509-3520 (2017) - 2016
- [j93]Davide Marano, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
Optimized Active Single-Miller Capacitor Compensation With Inner Half-Feedforward Stage for Very High-Load Three-Stage OTAs. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(9): 1349-1359 (2016) - [c144]Davide Marano, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
A 0.003-mm2 50-mW three-stage amplifier driving 10-nF with 2.7-MHz GBW. ICECS 2016: 728-731 - [c143]Gianluca Giustolisi, Gaetano Palumbo, Paolo Finocchiaro, Alfio Pappalardo:
Verilog-a modeling of Silicon Photo-Multipliers. ISCAS 2016: 1270-1273 - 2015
- [j92]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Variations in Nanometer CMOS Flip-Flops: Part II - Energy Variability and Impact of Other Sources of Variations. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3): 835-843 (2015) - [j91]Alfio Dario Grasso, Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
Design Methodology of Subthreshold Three-Stage CMOS OTAs Suitable for Ultra-Low-Power Low-Area and High Driving Capability. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(6): 1453-1462 (2015) - [j90]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Variations in Nanometer CMOS Flip-Flops: Part I - Impact of Process Variations on Timing. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2035-2043 (2015) - [j89]Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
High-Performance Four-Stage CMOS OTA Suitable for Large Capacitive Loads. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(10): 2476-2484 (2015) - [j88]Gianluca Giustolisi, Gaetano Palumbo:
Three-Stage Dynamic-Biased CMOS Amplifier With a Robust Optimization of the Settling Time. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(11): 2641-2651 (2015) - [j87]Gianluca Giustolisi, Alfio Dario Grasso, Gaetano Palumbo:
Integrated Quenching-and-Reset Circuit for Single-Photon Avalanche Diodes. IEEE Trans. Instrum. Meas. 64(1): 271-277 (2015) - [c142]Massimo Alioto, Gaetano Palumbo, Elio Consoli:
PVT variations in differential flip-flops: A comparative analysis. ECCTD 2015: 1-4 - [c141]Giuseppe Di Cataldo, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
Single-miller all-passive compensation network for three-stage OTAs. ECCTD 2015: 1-4 - [c140]Alfio Dario Grasso, Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
195-nW 120-dB subthreshold CMOS OTA driving up to 200 pF and occupying only 4.4-10-3 mm2. ICECS 2015: 65-68 - [c139]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Comparative analysis of the robustness of master-slave flip-flops against variations. ICECS 2015: 117-120 - [c138]Massimo Alioto, Gaetano Palumbo, Elio Consoli:
Variability budgetin pulsed flip-flops. NEWCAS 2015: 1-4 - [c137]Davide Marano, Giovanni Bonanno, S. Garozzo, Giuseppe Romeo, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
A new enhanced PSPICE implementation of the equivalent circuit model of SiPM detectors. NEWCAS 2015: 1-4 - 2014
- [j86]Alfio Dario Grasso, Davide Marano, Fermin Esparza-Alfaro, Antonio J. López-Martín, Gaetano Palumbo, Salvatore Pennisi:
Self-Biased Dual-Path Push-Pull Output Buffer Amplifier for LCD Column Drivers. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(3): 663-670 (2014) - [j85]Fermin Esparza-Alfaro, Salvatore Pennisi, Gaetano Palumbo, Antonio J. López-Martín:
Low-Power Class-AB CMOS Voltage Feedback Current Operational Amplifier With Tunable Gain and Bandwidth. IEEE Trans. Circuits Syst. II Express Briefs 61-II(8): 574-578 (2014) - [j84]Elio Consoli, Gaetano Palumbo, Jan M. Rabaey, Massimo Alioto:
Novel Class of Energy-Efficient Very High-Speed Conditional Push-Pull Pulsed Latches. IEEE Trans. Very Large Scale Integr. Syst. 22(7): 1593-1605 (2014) - [c136]Gianluca Giustolisi, Alfio Dario Grasso, Gaetano Palumbo:
Monolithic quenching-and-reset circuit for single-photon avalanche diodes. ICECS 2014: 76-79 - [c135]Fermin Esparza-Alfaro, Antonio J. López-Martín, Gaetano Palumbo, Salvatore Permisi:
CMOS class-AB tunable voltage-feedback current operational amplifier. ICECS 2014: 140-143 - [c134]Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi, Giuseppe Di Cataldo:
High-performance frequency compensation topology for four-stage OTAs. ICECS 2014: 211-214 - [c133]Davide Marano, Giovanni Bonanno, Massimiliano Belluso, Sergio Billotta, Alessandro Grillo, S. Garozzo, Giuseppe Romeo, Alfio Dario Grasso, Salvatore Pennisi, Gaetano Palumbo:
A new accurate analytical expression for the SiPM transient response to single photons. ICECS 2014: 514-517 - 2013
- [c132]Gianluca Giustolisi, Gaetano Palumbo, Paolo Finocchiaro, Alfio Pappalardo:
A simple extraction procedure for determining the electrical parameters in Silicon Photomultipliers. ECCTD 2013: 1-4 - [c131]Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
Optimized frequency compensation topology for low-power three-stage OTAs. ECCTD 2013: 1-4 - 2012
- [j83]Gianluca Giustolisi, Rosario Mita, Gaetano Palumbo:
Behavioral modeling of statistical phenomena of single-photon avalanche diodes. Int. J. Circuit Theory Appl. 40(7): 661-679 (2012) - [j82]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
From energy-delay metrics to constraints on the design of digital circuits. Int. J. Circuit Theory Appl. 40(8): 815-834 (2012) - [j81]Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo:
An Accurate Ultra-Compact I-V Model for Nanometer MOS Transistors With Applications on Digital Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(1): 159-169 (2012) - [j80]Gianluca Giustolisi, Gaetano Palumbo, Ester Spitale:
Robust Miller Compensation With Current Amplifiers Applied to LDO Voltage Regulators. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(9): 1880-1893 (2012) - [j79]Gaetano Palumbo, Melita Pennisi, Massimo Alioto:
A Simple Circuit Approach to Reduce Delay Variations in Domino Logic Gates. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(10): 2292-2300 (2012) - [j78]Elio Consoli, Gaetano Palumbo, Melita Pennisi:
Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master-Slave Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 20(2): 284-295 (2012) - [c130]Massimo Alioto, Gaetano Palumbo, Melita Pennisi:
A simple keeper topology to reduce delay variations in nanometer domino logic. ISCAS 2012: 1576-1579 - [c129]Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo:
Logic gates dynamic modeling by means of an ultra-compact MOS model. ISCAS 2012: 3250-3253 - [c128]Elio Consoli, Massimo Alioto, Gaetano Palumbo, Jan M. Rabaey:
Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS. ISSCC 2012: 482-484 - 2011
- [j77]Massimo Alioto, Gaetano Palumbo, Massimo Poli:
Optimized design of parallel carry-select adders. Integr. 44(1): 62-74 (2011) - [j76]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies. IEEE Trans. Very Large Scale Integr. Syst. 19(5): 725-736 (2011) - [j75]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit. IEEE Trans. Very Large Scale Integr. Syst. 19(5): 737-750 (2011) - [c127]Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo:
Inverter transfer curves and SRAM noise margin evaluation based on an ultra-compact MOS model. ECCTD 2011: 512-515 - [c126]Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo:
An ultra-compact MOS model in nanometer technologies. ECCTD 2011: 520-523 - [c125]Gaetano Palumbo, Melita Pennisi, Ramón González Carvajal:
Figures of merit for class AB input stages. ECCTD 2011: 749-752 - [c124]Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
Self-biased dual-path push-pull output buffer amplifier topology for LCD driver applications. ISCAS 2011: 29-32 - [c123]Elio Consoli, Gaetano Palumbo, Melita Pennisi:
TG Master-Slave FFs: High-speed optimization. ISCAS 2011: 554-557 - [c122]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
DET FF topologies: A detailed investigation in the energy-delay-area domain. ISCAS 2011: 563-566 - [c121]Gianluca Giustolisi, Rosario Mita, Gaetano Palumbo:
Verilog-A modeling of SPAD statistical phenomena. ISCAS 2011: 773-776 - 2010
- [j74]Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
Step-response optimisation techniques for low-power, high-load, three-stage operational amplifiers driving large capacitive loads. IET Circuits Devices Syst. 4(2): 87-98 (2010) - [j73]Alfio Dario Grasso, Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
Analytical comparison of reversed nested Miller frequency compensation techniques. Int. J. Circuit Theory Appl. 38(7): 709-737 (2010) - [j72]Massimo Alioto, Gaetano Palumbo, Massimo Poli:
Simple and accurate modeling of the output transition time in nanometer CMOS gates. Int. J. Circuit Theory Appl. 38(10): 995-1012 (2010) - [j71]Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
Improved Low-Power High-Speed Buffer amplifier with slew-Rate Enhancement for LCD Applications. J. Circuits Syst. Comput. 19(2): 325-334 (2010) - [j70]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(6): 1273-1286 (2010) - [j69]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7): 1583-1596 (2010) - [j68]Massimo Alioto, Gaetano Palumbo, Melita Pennisi:
Understanding the Effect of Process Variations on the Delay of Static and Domino Logic. IEEE Trans. Very Large Scale Integr. Syst. 18(5): 697-710 (2010) - [c120]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency. ISCAS 2010: 321-324 - [c119]Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
Analytical figure of merit evaluation of RNMC networks for low-power three-stage OTAs. ISCAS 2010: 777-780 - [c118]Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
A novel low-power high-speed rail-to-rail class-B buffer amplifier for LCD output drivers. ISCAS 2010: 2816-2819 - [c117]Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
Low-power dual-active class-AB buffer amplifier with self-biasing network for LCD column drivers. ISCAS 2010: 2832-2835 - [c116]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits. PATMOS 2010: 62-72
2000 – 2009
- 2009
- [j67]Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi:
Approach to analyse and design nearly sinusoidal oscillators. IET Circuits Devices Syst. 3(4): 204-221 (2009) - [j66]Rosario Mita, Gaetano Palumbo:
Propagation delay of an RC-circuit with a ramp input: An analytical very accurate and simple model. Int. J. Circuit Theory Appl. 37(9): 987-994 (2009) - [j65]Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
Improved Power-Efficient RNMC Technique with voltage Buffer and Nulling resistors for Low-Power High-Load Three-Stage amplifiers. J. Circuits Syst. Comput. 18(7): 1321-1331 (2009) - [j64]Massimo Alioto, Gaetano Palumbo, Massimo Poli:
Analysis and Modeling of Energy Consumption in RLC Tree Circuits. IEEE Trans. Very Large Scale Integr. Syst. 17(2): 278 (2009) - [c115]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Impact of clock slope on energy/delay of pulsed flip-flops and optimum clock domain design. ECCTD 2009: 61-64 - [c114]Massimo Alioto, Elio Consoli, Gaetano Palumbo, Melita Pennisi:
Correct procedures to evaluate the effect of intradie variations on the delay variability of digital circuits. ECCTD 2009: 779-782 - [c113]Massimo Alioto, Gaetano Palumbo, Melita Pennisi:
Analysis of the impact of random process variations in CMOS tapered buffers. ICECS 2009: 57-60 - [c112]Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
An efficient RNM compensation topology with voltage buffer and nulling resistors for large-capacitive-load three-stage OTAs. ICECS 2009: 128-131 - [c111]Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
A high-speed low-power output buffer amplifier for large-size LCD applications. ICECS 2009: 132-135 - [c110]Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi:
Exploitation of the phasor approach for closed-form solution of the Van der Pol's oscillator and sinusoidal oscillators with high-order nonlinearity. ICECS 2009: 155-158 - [c109]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Optimum clock slope for flip-flops within a clock domain: Analysis and a case study. ICECS 2009: 275-278 - [c108]Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
Step-response Optimization Techniques for Low-power Three-stage Operational Amplifiers for Large Capacitive Load Applications. ISCAS 2009: 1949-1952 - [c107]Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
A New Advanced RNMC Technique with Dual-active Current and Voltage Buffers for Low-power High-load Three-stage Amplifiers. ISCAS 2009: 2725-2728 - [c106]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Metrics and Design Considerations on the Energy-delay Tradeoff of Digital Circuits. ISCAS 2009: 3150-3153 - 2008
- [j63]Rosario Mita, Gaetano Palumbo, Pier Giorgio Fallica:
Accurate model for single-photon avalanche diodes. IET Circuits Devices Syst. 2(2): 207-212 (2008) - [j62]Walter Aloisi, Gaetano Palumbo, Salvatore Pennisi:
Design methodology of Miller frequency compensation with current buffer/amplifier. IET Circuits Devices Syst. 2(2): 227-233 (2008) - [j61]Salvatore Omar Cannizzaro, Gaetano Palumbo, Salvatore Pennisi:
An approach to model high-frequency distortion in negative-feedback amplifiers. Int. J. Circuit Theory Appl. 36(1): 3-18 (2008) - [j60]Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
Analytical comparison of frequency compensation techniques in three-stage amplifiers. Int. J. Circuit Theory Appl. 36(1): 53-80 (2008) - [j59]Salvatore Omar Cannizzaro, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
Single Miller capacitor frequency compensation with nulling resistor for three-stage amplifiers. Int. J. Circuit Theory Appl. 36(7): 825-837 (2008) - [j58]Gaetano Palumbo, Melita Pennisi:
AMOLED pixel driver circuits based on poly-Si TFTs: A comparison. Integr. 41(3): 439-446 (2008) - [j57]Massimo Alioto, Gaetano Palumbo:
Power-Aware Design of Nanometer MCML Tapered Buffers. IEEE Trans. Circuits Syst. II Express Briefs 55-II(1): 16-20 (2008) - [j56]Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi:
Wien-Type Oscillators: Evaluation and Optimization of Harmonic Distortion. IEEE Trans. Circuits Syst. II Express Briefs 55-II(7): 628-632 (2008) - [j55]Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi:
Miller Theorem for Weakly Nonlinear Feedback Circuits and Application to CE Amplifier. IEEE Trans. Circuits Syst. II Express Briefs 55-II(10): 991-995 (2008) - [j54]Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
Comparison of the Frequency Compensation Techniques for CMOS Two-Stage Miller OTAs. IEEE Trans. Circuits Syst. II Express Briefs 55-II(11): 1099-1103 (2008) - [j53]Rosario Mita, Gaetano Palumbo:
High-Speed and Compact Quenching Circuit for Single-Photon Avalanche Diodes. IEEE Trans. Instrum. Meas. 57(3): 543-547 (2008) - [c105]Massimo Alioto, Gaetano Palumbo, Melita Pennisi:
Analysis of the impact of process variations on static logic circuits versus fan-in. ICECS 2008: 137-140 - [c104]Gaetano Palumbo, Melita Pennisi:
Design guidelines for high-speed Transmission-gate latches: Analysis and comparison. ICECS 2008: 145-148 - [c103]Massimo Alioto, Gaetano Palumbo, Massimo Poli:
Energy evaluation in RLC tree circuits with exponential input. ICECS 2008: 578-581 - [c102]Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi:
Design guidelines for minimum harmonic distortion in a wien oscillator with automatic amplitude control system. ICECS 2008: 1127-1130 - [c101]Massimo Alioto, Gaetano Palumbo:
Power-delay optimization in MCML tapered buffers. ISCAS 2008: 141-144 - [c100]Gianluca Giustolisi, Gaetano Palumbo, Ester Spitale:
Low-voltage LDO Compensation Strategy based on Current Amplifiers. ISCAS 2008: 2681-2684 - [c99]Massimo Alioto, Massimo Poli, Gaetano Palumbo:
Explicit energy evaluation in RLC tree circuits with ramp inputs. ISCAS 2008: 2865-2868 - [c98]Massimo Alioto, Gaetano Palumbo, Melita Pennisi:
Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic. PATMOS 2008: 136-145 - 2007
- [j52]Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo:
Mixed Full Adder topologies for high-performance low-power arithmetic circuits. Microelectron. J. 38(1): 130-139 (2007) - [j51]Rosario Mita, Gaetano Palumbo, Massimo Poli:
Propagation Delay of an RC-Chain With a Ramp Input. IEEE Trans. Circuits Syst. II Express Briefs 54-II(1): 66-70 (2007) - [j50]Arnaldo D'Amico, Christian Falconi, Gianluca Giustolisi, Gaetano Palumbo:
Resistance of Feedback Amplifiers: A Novel Representation. IEEE Trans. Circuits Syst. II Express Briefs 54-II(4): 298-302 (2007) - [j49]Alfio Dario Grasso, Davide Marano, Gaetano Palumbo, Salvatore Pennisi:
Improved Reversed Nested Miller Frequency Compensation Technique With Voltage Buffer and Resistor. IEEE Trans. Circuits Syst. II Express Briefs 54-II(5): 382-386 (2007) - [j48]Salvatore Omar Cannizzaro, Alfio Dario Grasso, Rosario Mita, Gaetano Palumbo, Salvatore Pennisi:
Design Procedures for Three-Stage CMOS OTAs With Nested-Miller Compensation. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(5): 933-940 (2007) - [j47]Massimo Alioto, Gaetano Palumbo:
Interconnect-Aware Design of Fast Large Fan-In CMOS Multiplexers. IEEE Trans. Circuits Syst. II Express Briefs 54-II(6): 484-488 (2007) - [j46]Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
Advances in Reversed Nested Miller Compensation. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(7): 1459-1470 (2007) - [c97]Gianluca Giustolisi, Gaetano Palumbo, Ester Spitale:
LDO compensation strategy based on current buffer/amplifiers. ECCTD 2007: 116-119 - [c96]Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi:
Distortion analysis in the frequency domain of a Gm-C biquad. ECCTD 2007: 212-215 - [c95]Giuseppe Di Cataldo, Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi:
A generalization of Miller formulae for nonlinear feedback networks. ECCTD 2007: 224-227 - [c94]Salvatore Omar Cannizzaro, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
Single Miller capacitor frequency compensation with nulling resistor for three-stage amplifiers. ECCTD 2007: 643-646 - [c93]Rosario Mita, Gaetano Palumbo:
Highly-accurate propagation delay analytical model of an RC-circuit with a ramp input. ECCTD 2007: 667-670 - [c92]Massimo Alioto, Gaetano Palumbo, Massimo Poli:
Energy consumption in RLC tree circuits. ECCTD 2007: 771-774 - [c91]Massimo Alioto, Gaetano Palumbo:
Very high-speed carry computation based on mixed dynamic/transmission-gate Full Adders. ECCTD 2007: 799-802 - [c90]Massimo Alioto, Massimo Poli, Gaetano Palumbo:
Efficient and Accurate Models of Output Transition Time in CMOS Logic. ICECS 2007: 1264-1267 - [c89]Christian Falconi, Arnaldo D'Amico, Gianluca Giustolisi, Gaetano Palumbo:
Rosenstark-like Representation of Feedback Amplifier Resistance. ISCAS 2007: 2212-2215 - [c88]Walter Aloisi, Giuseppe Di Cataldo, Gaetano Palumbo, Salvatore Pennisi:
Miller Compensation: Optimization with Current Buffer/Amplifier. ISCAS 2007: 2216-2219 - [c87]Massimo Alioto, Gaetano Palumbo:
High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology. ISCAS 2007: 2998-3001 - [c86]Massimo Alioto, Gaetano Palumbo:
Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects. ISCAS 2007: 3255-3258 - [c85]Massimo Alioto, Gaetano Palumbo:
Delay Variability Due to Supply Variations in Transmission-Gate Full Adders. ISCAS 2007: 3732-3735 - 2006
- [j45]Rosario Mita, Gaetano Palumbo, Pier Giorgio Fallica:
A fast driver circuit for single-photon sensors. Microelectron. J. 37(10): 1092-1096 (2006) - [j44]Massimo Alioto, Gaetano Palumbo:
Design strategies of cascaded CML gates. IEEE Trans. Circuits Syst. II Express Briefs 53-II(2): 85-89 (2006) - [j43]Gaetano Palumbo, Domenico Pappalardo:
Charge pump circuits with only capacitive loads: optimized design. IEEE Trans. Circuits Syst. II Express Briefs 53-II(2): 128-132 (2006) - [j42]Salvatore Omar Cannizzaro, Gaetano Palumbo, Salvatore Pennisi:
Effects of nonlinear feedback in the frequency domain. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(2): 225-234 (2006) - [j41]Salvatore Omar Cannizzaro, Gaetano Palumbo, Salvatore Pennisi:
Distortion analysis of Miller-compensated three-stage amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(5): 961-976 (2006) - [j40]Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
Three-Stage CMOS OTA for Large Capacitive Loads With Efficient Frequency Compensation Scheme. IEEE Trans. Circuits Syst. II Express Briefs 53-II(10): 1044-1048 (2006) - [j39]Massimo Alioto, Rosario Mita, Gaetano Palumbo:
Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers. IEEE Trans. Circuits Syst. II Express Briefs 53-II(11): 1165-1169 (2006) - [j38]Massimo Alioto, Gaetano Palumbo, Massimo Poli:
Energy Consumption in RC Tree Circuits. IEEE Trans. Very Large Scale Integr. Syst. 14(5): 452-461 (2006) - [j37]Massimo Alioto, Gaetano Palumbo:
Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison. IEEE Trans. Very Large Scale Integr. Syst. 14(12): 1322-1335 (2006) - [c84]Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi:
Analysis of Harmonic Distortion in the Colpitts Oscillator. ICECS 2006: 196-199 - [c83]Gianluca Giustolisi, Gaetano Palumbo, Christian Falconi, Arnaldo D'Amico:
NMOS Low Drop-Out Regulator with Dynamic Biasing. ICECS 2006: 204-207 - [c82]Massimo Alioto, Gaetano Palumbo:
Modeling of Delay Variability Due to Supply Variations in Pass-Transistor and Static Full Adders. ICECS 2006: 518-521 - [c81]Giuseppe Di Cataldo, Rosario Mita, Gaetano Palumbo, Massimo Poli:
RC-Chain: a Simple Model of Delay with a Ramp Input. ICECS 2006: 557-560 - [c80]Giuseppe Di Cataldo, Rosario Mita, Gaetano Palumbo, Melita Pennisi:
Modeling of Feedback Analog Circuits with VHDL. ICECS 2006: 882-885 - [c79]Massimo Alioto, Rosario Mita, Gaetano Palumbo:
A Design Methodology for High-Speed Low-Power MCML Frequency Dividers. ICECS 2006: 1308-1311 - [c78]Massimo Alioto, Gaetano Palumbo:
Delay uncertainty due to supply variations in static and dynamic full adders. ISCAS 2006 - [c77]Massimo Alioto, Gaetano Palumbo:
Nanometer MCML gates: models and design considerations. ISCAS 2006 - [c76]Massimo Alioto, Gaetano Palumbo, Massimo Poli:
Efficient output transition time modeling in CMOS gates with ramp/exponential inputs. ISCAS 2006 - [c75]Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
Active reversed nested Miller compensation for three-stage amplifiers. ISCAS 2006 - [c74]Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi:
Analysis and evaluation of harmonic distortion in the tunnel diode oscillator. ISCAS 2006 - 2005
- [j36]Massimo Alioto, Gaetano Palumbo:
Power-delay optimization of D-latch/MUX source coupled logic gates. Int. J. Circuit Theory Appl. 33(1): 65-86 (2005) - [j35]Walter Aloisi, Gaetano Palumbo:
Efficiency model of boost dc-dc PWM converters. Int. J. Circuit Theory Appl. 33(5): 419-432 (2005) - [j34]Massimo Alioto, Gaetano Palumbo:
Modelling and design considerations on CML gates under high-current effects. Int. J. Circuit Theory Appl. 33(6): 503-518 (2005) - [j33]Antonino Conte, Gianbattista Lo Giudice, Gaetano Palumbo, Alfredo Signorello:
A high-performance very low-voltage current sense amplifier for nonvolatile memories. IEEE J. Solid State Circuits 40(2): 507-514 (2005) - [j32]Rosario Mita, Gaetano Palumbo, Salvatore Pennisi:
Nonidealities of Tow-Thomas biquads Using VOA- and CFOA-based Miller integrators. IEEE Trans. Circuits Syst. II Express Briefs 52-II(1): 22-27 (2005) - [j31]Rosario Mita, Gaetano Palumbo, Salvatore Pennisi:
Low-voltage high-drive CMOS current feedback op-amp. IEEE Trans. Circuits Syst. II Express Briefs 52-II(6): 317-321 (2005) - [j30]Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo:
Design and Comparison of Very Low-Voltage CMOS Output Stages. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(8): 1545-1556 (2005) - [c73]Salvatore Omar Cannizzaro, Gaetano Palumbo, Salvatore Pennisi:
Distortion analysis of three-stage amplifiers with reversed nested-Miller compensation. ECCTD 2005: 93-96 - [c72]Salvatore Omar Cannizzaro, Gaetano Palumbo, Salvatore Pennisi:
New analytical approach to evaluate harmonic distortion in nonlinear feedback amplifiers. ECCTD 2005: 97-100 - [c71]Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo:
Guidelines for designing class-AB output stages. ECCTD 2005: 109-112 - [c70]Alfio Dario Grasso, Gaetano Palumbo:
Optimized design of ECL gates with a power constraint. ECCTD 2005: 221-224 - [c69]Gianluca Giustolisi, Gaetano Palumbo, Maurizio Gaibotti, Michelangelo Pisasale:
Statistical analysis of CMOS current reference. ECCTD 2005: 341-344 - [c68]Rosario Mita, Gaetano Palumbo, Giorgio Fallica:
A fast active quenching and recharging circuit for single-photon avalanche diodes. ECCTD 2005: 385-388 - [c67]Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo:
Analysis and optimization of a low-voltage class-AB output stage. ICECS 2005: 1-4 - [c66]Gianluca Giustolisi, Gaetano Palumbo:
Comparison of methods for predicting distortion in class-AB stages. ICECS 2005: 1-4 - [c65]Rosario Mita, Andrea Oliveri, Gaetano Palumbo, Pier Giorgio Fallica:
A novel model for single photon detectors. ICECS 2005: 1-4 - [c64]Rosario Mita, Gaetano Palumbo:
VHDL-based modeling of a DC-DC boost converter. ICECS 2005: 1-4 - [c63]Rosario Mita, Gaetano Palumbo, Melita Pennisi:
Behavioral model of charge pumps with VHDL. ICECS 2005: 1-4 - [c62]Gaetano Palumbo, Melita Pennisi:
A comparison between amoled poly-TFT driver circuits. ICECS 2005: 1-5 - [c61]Gaetano Palumbo, Domenico Pappalardo, Luigi Innacolo:
Design strategy to minimize rise time and silicon area of charge pump with only capacitive loads. ICECS 2005: 1-4 - [c60]Rosario Mita, Gaetano Palumbo, Salvatore Pennisi:
Well-defined design procedure for a three-stage CMOS OTA. ISCAS (3) 2005: 2579-2582 - [c59]Gaetano Palumbo, Pasquale Tommasino, Alessandro Trifiletti:
Optimized design of source coupled logic gates in GaAs HEMT technology. ISCAS (4) 2005: 3583-3586 - [c58]Massimo Alioto, Gaetano Palumbo:
Design techniques for low-power cascaded CML gates. ISCAS (5) 2005: 4685-4688 - [c57]Massimo Alioto, Gaetano Palumbo, Massimo Poli:
Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model. PATMOS 2005: 355-363 - 2004
- [j29]Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo:
Exploiting the high-frequency performance of low-voltage low-power SC filters. IEEE Trans. Circuits Syst. II Express Briefs 51-II(2): 77-84 (2004) - [j28]Rosario Mita, Gaetano Palumbo, Salvatore Pennisi:
Effect of CFOA nonidealities in Miller integrator cells. IEEE Trans. Circuits Syst. II Express Briefs 51-II(5): 249-253 (2004) - [j27]Massimo Alioto, Gaetano Palumbo, Massimo Poli:
Evaluation of energy consumption in RC ladder circuits driven by a ramp input. IEEE Trans. Very Large Scale Integr. Syst. 12(10): 1094-1107 (2004) - [c56]Antonino Conte, Gianbattista Lo Giudice, Gaetano Palumbo, Alfredo Signorello:
A 1.35-V sense amplifier for non volatile memories based on current mode approach. ESSCIRC 2004: 471-474 - [c55]Walter Aloisi, Stello Matteo Billé, Gaetano Palumbo:
Low-voltage linear voltage regulator suitable for memories. ISCAS (1) 2004: 389-392 - [c54]Massimo Alioto, Gaetano Palumbo, Massimo Poli:
A gate-level strategy to design Carry Select Adders. ISCAS (2) 2004: 465-468 - [c53]Gaetano Palumbo, Salvatore Pennisi:
Harmonic distortion in three-stage nested-Miller-compensated amplifiers. ISCAS (1) 2004: 485-488 - [c52]Gianluca Giustolisi, Gaetano Palumbo:
Sigma-Delta A/D fuzzy converter. ISCAS (4) 2004: 677-680 - 2003
- [j26]Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo:
Analysis, modelling and optimization of a gain boosted telescopic amplifier. Int. J. Circuit Theory Appl. 31(5): 513-528 (2003) - [j25]Massimo Alioto, Rosario Mita, Gaetano Palumbo:
Performance evaluation of the low-voltage CML D-latch topology. Integr. 36(4): 191-209 (2003) - [j24]Gianluca Giustolisi, Gaetano Palumbo, M. Criscione, F. Cutri:
A low-voltage low-power voltage reference based on subthreshold MOSFETs. IEEE J. Solid State Circuits 38(1): 151-154 (2003) - [j23]Rosario Mita, Gaetano Palumbo, Salvatore Pennisi:
1.5-V CMOS CCII+ with high current-driving capability. IEEE Trans. Circuits Syst. II Express Briefs 50(4): 187-190 (2003) - [j22]Rosario Mita, Gaetano Palumbo, Salvatore Pennisi:
Design guidelines for reversed nested Miller compensation in three-stage amplifiers. IEEE Trans. Circuits Syst. II Express Briefs 50(5): 227-233 (2003) - [c51]Gianluca Giustolisi, Gaetano Palumbo:
A novel 1-V class-AB transconductor for improving speed performance in SC applications. ISCAS (1) 2003: 153-156 - [c50]Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo:
A 1-V CMOS output stage with high linearity. ISCAS (1) 2003: 225-228 - [c49]Gianluca Giustolisi, Gaetano Palumbo:
A new method for evaluating harmonic distortion in push-pull output stages. ISCAS (1) 2003: 233-236 - [c48]Massimo Alioto, Gaetano Palumbo:
Design of MUX, XOR and D-latch SCL gates. ISCAS (5) 2003: 261-264 - [c47]Rosario Mita, Gaetano Palumbo, Salvatore Pennisi:
Performance comparison of Tow-Thomas biquad filters based on VOAs and CFOAs. ISCAS (1) 2003: 525-528 - [c46]Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo:
Design of low-voltage low-power SC filters for high-frequency applications. ISCAS (1) 2003: 605-608 - 2002
- [j21]Massimo Alioto, Gaetano Palumbo, Salvatore Pennisi:
Modelling of source-coupled logic gates. Int. J. Circuit Theory Appl. 30(4): 459-477 (2002) - [j20]Gianluca Giustolisi, Gaetano Palumbo, Salvatore Pennisi:
Current-mode A/D fuzzy converter. IEEE Trans. Fuzzy Syst. 10(4): 533-540 (2002) - [j19]Massimo Alioto, Gaetano Palumbo:
Analysis and comparison on full adder block in submicron technology. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 806-823 (2002) - [c45]Giuseppe Notarangelo, Marco Gibilaro, Francesco Pappalardo, Agatino Pennisi, Gaetano Palumbo:
Low Power Strategy for a TFT Controller. DSD 2002: 351-354 - [c44]Gianluca Giustolisi, Gaetano Palumbo, Salvatore Pennisi:
Statistical analysis of the resolution in a current-mode ADC. ICECS 2002: 5-8 - [c43]Gaetano Palumbo, Domenico Pappalardo, Maurizio Gaibotti:
Voltage regulator based on an high-efficiency adaptive charge pump. ICECS 2002: 61-64 - [c42]Rosario Mita, Gaetano Palumbo, Salvatore Pennisi:
Hybrid nested Miller compensation with nulling resistors. ICECS 2002: 177-180 - [c41]Rosario Mita, Gaetano Palumbo, Salvatore Pennisi:
Comparison between Miller integrator cells using VOAs and CFOAs. ICECS 2002: 181-184 - [c40]Rosario Mita, Gaetano Palumbo, Salvatore Pennisi, Massimo Poli:
A novel pseudo random bit generator for cryptography applications. ICECS 2002: 489-492 - [c39]Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo:
Design guidelines for bipolar frequency dividers. ICECS 2002: 521-524 - [c38]L. De Ambrogi, S. Nicosia, Giovanni Pagano, Gaetano Palumbo:
A high-performance buffer for non-volatile memories. ICECS 2002: 611-614 - [c37]Gaetano Palumbo, Massimo Poli:
Propagation delay model of current driven RC chain. ICECS 2002: 619-622 - [c36]Massimo Alioto, Rosario Mita, Gaetano Palumbo:
Analysis and comparison of low-voltage CML D-latch. ICECS 2002: 737-740 - [c35]Gaetano Palumbo, Francesco Pappalardo, S. Sannella:
Evaluation on power reduction applying gated clock approaches. ISCAS (4) 2002: 85-88 - [c34]Massimo Alioto, Gaetano Palumbo:
Power-delay trade-offs in SCL gates. ISCAS (3) 2002: 249-252 - [c33]Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo:
Analysis and optimization of gain-boosted telescopic amplifiers. ISCAS (1) 2002: 321-324 - [c32]Gianluca Giustolisi, Gaetano Palumbo:
Analysis of power supply noise attenuation in a PTAT current source. ISCAS (1) 2002: 561-564 - [c31]Massimo Alioto, Gaetano Palumbo, Massimo Poli:
An Approach to Energy Consumption Modeling in RC Ladder Circuits. PATMOS 2002: 239-246 - [c30]Massimo Alioto, Gaetano Palumbo:
Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates. PATMOS 2002: 429-437 - [c29]Rosario Mita, Gaetano Palumbo:
Modeling of Propagation Delay of a First Order Circuit with a Ramp Input. PATMOS 2002: 468-476 - 2001
- [j18]Gianluca Giustolisi, Giuseppe Palmisano, Gaetano Palumbo:
Analysis and optimization of a novel CMOS multiplier. Int. J. Circuit Theory Appl. 29(3): 321-330 (2001) - [j17]Gaetano Palumbo, Salvatore Pennisi:
A high‐performance CMOS CCII. Int. J. Circuit Theory Appl. 29(3): 331-336 (2001) - [j16]Massimo Alioto, Gaetano Palumbo:
Power estimation in adiabatic circuits: a simple and accurate model. IEEE Trans. Very Large Scale Integr. Syst. 9(5): 608-615 (2001) - [c28]Gaetano Palumbo, Salvatore Pennisi:
Feedback amplifiers: a simplified analysis of harmonic distortion in the frequency domain. ICECS 2001: 209-212 - [c27]Massimo Alioto, Gaetano Palumbo, Salvatore Pennisi:
Delay estimation of SCL gates with output buffer. ICECS 2001: 719-722 - [c26]Massimo Alioto, Gaetano Palumbo:
Optimized design of high fan-in multiplexers using switches with driving capability. ICECS 2001: 737-740 - [c25]M. Criscione, Gianluca Giustolisi, A. Lionetto, M. Muscarà, Gaetano Palumbo:
A fuzzy controller for step-up DC/DC converters. ICECS 2001: 977-980 - [c24]Gaetano Palumbo, Giuseppe Introvaia, Vincenzo Mastrocola, Promod Kumar, Francesco Pipiton:
Built-In Self Test for Low Cost Testing of a 60 MHz Synchronous Flash Memory. IOLTW 2001: 192-196 - [c23]Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo:
CML ring oscillators: oscillation frequency. ISCAS (4) 2001: 112-115 - [c22]Rosario Mita, Gaetano Palumbo, Salvatore Pennisi:
Reversed nested Miller compensation with current follower. ISCAS (1) 2001: 308-311 - [c21]Gaetano Palumbo, Domenico Pappalardo, Maurizio Gaibotti:
Modeling and minimization of power consumption in charge pump circuits. ISCAS (4) 2001: 402-405 - [c20]Gianluca Giustolisi, Gaetano Palumbo:
Detailed frequency analysis of power supply rejection in Brokaw bandgap. ISCAS (1) 2001: 731-734 - 2000
- [j15]Gianluca Giustolisi, Giuseppe Palmisano, Gaetano Palumbo:
CMRR frequency response of CMOS operational transconductance amplifiers. IEEE Trans. Instrum. Meas. 49(1): 137-143 (2000) - [c19]Massimo Alioto, Gaetano Palumbo:
High-speed bipolar MUX modeling and design. ISCAS 2000: 1-4 - [c18]Gianluca Giustolisi, Giuseppe Palmisano, Gaetano Palumbo:
A fuzzy membership function circuit in SC technique. ISCAS 2000: 393-396 - [c17]Massimo Alioto, Gaetano Palumbo:
Evaluation of power consumption in adiabatic circuits. ISCAS 2000: 629-632 - [c16]Massimo Alioto, Gaetano Palumbo:
Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates. PATMOS 2000: 265-275
1990 – 1999
- 1999
- [j14]Massimo Alioto, Gaetano Palumbo:
Highly accurate and simple models for CML and ECL gates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9): 1369-1375 (1999) - [j13]Giuseppe Di Cataldo, Giuseppe Palmisano, Gaetano Palumbo, Salvatore Pennisi:
High-speed voltage buffers for the experimental characterization of CMOS transconductance operational amplifiers. IEEE Trans. Instrum. Meas. 48(1): 31-33 (1999) - [c15]Gaetano Palumbo, Salvatore Pennisi:
A class AB CMOS current mirror with low-voltage capability. ICECS 1999: 891-894 - [c14]Giuseppe Palmisano, Gaetano Palumbo, Salvatore Pennisi:
Performance parameters of current operational amplifiers. ICECS 1999: 1615-1618 - [c13]Gaetano Palumbo, Davide Torrisi, Riccardo Ursino:
A general HDL-A model of a DC-DC switching regulator core. ICECS 1999: 1663-1666 - 1998
- [j12]Gaetano Palumbo, Salvatore Pennisi:
Harmonic distortion in non-linear amplifier with non-linear feedback. Int. J. Circuit Theory Appl. 26(3): 293-299 (1998) - [j11]Gaetano Palumbo:
A novel fully adjustable CMOS current Schmitt trigger with a 1·5 V power supply. Int. J. Circuit Theory Appl. 26(3): 323-327 (1998) - [j10]Giuseppe Palmisano, Gaetano Palumbo, Salvatore Pennisi:
High-drive CMOS current amplifier. IEEE J. Solid State Circuits 33(2): 228-236 (1998) - [c12]Gianluca Giustolisi, Giuseppe Palmisano, Gaetano Palumbo, C. Strano:
A Novel 1.5-V Cmos Mixer. Great Lakes Symposium on VLSI 1998: 113-117 - [c11]Massimo Alioto, Gaetano Palumbo:
Novel Simple Models Of Cml Propagation Delay. Great Lakes Symposium on VLSI 1998: 270-274 - [c10]Gaetano Palumbo, Salvatore Pennisi:
A high-performance CMOS voltage follower. ICECS 1998: 21-24 - [c9]Gaetano Palumbo, Salvatore Pennisi:
A technique for the reduction of the input resistance of current-mode circuits. ICECS 1998: 279-282 - [c8]Massimo Alioto, Gaetano Palumbo:
Design of CML gate with the best propagation delay. ICECS 1998: 287-290 - [c7]Gianluca Giustolisi, Giuseppe Palmisano, Gaetano Palumbo:
A 1.5 V CMOS voltage multiplier. ICECS 1998: 313-316 - 1996
- [j9]Giuseppe Di Cataldo, Gaetano Palumbo:
Area-efficient design of three- and four-stage voltage multipliers for power integrated circuits. Int. J. Circuit Theory Appl. 24(5): 541-550 (1996) - [c6]Giuseppe Palmisano, Gaetano Palumbo, Salvatore Pennisi:
Low harmonic distortion class AB CMOS current output stage. ICECS 1996: 5-8 - [c5]Giuseppe Palmisano, Gaetano Palumbo:
Simplified model of an amplifier with two poles and a pole-zero doublet. ICECS 1996: 124-127 - 1995
- [j8]G. Diutaldo, Gaetano Palumbo, Salvatore Pennisi:
A schmitt trigger by means of a ccii+. Int. J. Circuit Theory Appl. 23(2): 161-165 (1995) - [j7]Giuseppe Palmisano, Gaetano Palumbo:
A simple cmos CCII+. Int. J. Circuit Theory Appl. 23(6): 599-603 (1995) - [j6]Giovanni Calí, Giuseppe Palmisano, Gaetano Palumbo, N. Aiello:
An Area Efficient Current limiter for Automotive IC: Analysis and Design. J. Circuits Syst. Comput. 5(3): 443-454 (1995) - [c4]Giuseppe Di Cataldo, Giuseppe Palmisano, Gaetano Palumbo:
A CMOS CCII+. ISCAS 1995: 315-318 - 1994
- [j5]Giuseppe Palmisano, Gaetano Palumbo, Victor da Fonte Dias:
A high-frequency differential sc integrator with highly accurate gain compensation. Int. J. Circuit Theory Appl. 22(1): 71-75 (1994) - [j4]Gaetano Palumbo:
Cmos current comparator: Simplified analysis of the delay time. Int. J. Circuit Theory Appl. 22(2): 157-162 (1994) - [j3]Giuseppe Di Cataldo, Gaetano Palumbo:
Double and triple charge pumps with mos diodes: Dynamic models to an optimized design. Int. J. Circuit Theory Appl. 22(5): 377-386 (1994) - [j2]Giuseppe Di Cataldo, Gaetano Palumbo:
Improved dynamic model of double and triple charge pumps to take current leakage into account. Int. J. Circuit Theory Appl. 22(5): 419-423 (1994) - [c3]Gaetano Palumbo:
Design of the Wilson and Improved Wilson MOS Current Mirrors to Reach the Best Settling time. ISCAS 1994: 413-416 - [c2]Giuseppe Di Cataldo, Gaetano Palumbo:
Optimized Design of 4 Stage Dickson Voltage Multiplier. ISCAS 1994: 693-696 - [c1]Giuseppe Palmisano, Gaetano Palumbo, Salvatore Pennisi:
A High-Accuracy High-Speed CMOS Current Comparator. ISCAS 1994: 739-742 - 1993
- [j1]Giuseppe Di Cataldo, Gaetano Palumbo, S. Stivala:
New CMOS current mirrors with improved high-frequency response. Int. J. Circuit Theory Appl. 21(5): 443-450 (1993)
Coauthor Index
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