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ORCIDDSD 2003: Belek-Antalya, Turkey
- 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), Architectures, Methods and Tools, 3-5 September 2003, Belek-Antalya, Turkey. IEEE Computer Society 2003, ISBN 0-7695-2003-0
Keynote Speeches
- Gordon J. Brebner
:
Eccentric SoC Architectures as the Future Norm. 2-9 - Axel Jantsch:
NoCs: A new Contract between Hardware and Software. 10-16 - Hiroto Yasuura:
Towards the Digitally Named World -Challenges for New Social Infrastructures based on Information Technologies. 17-22 - Peter Petrov, Alex Orailoglu:
Customizable Embedded Processor Architectures. 468-475
Processor and Memory Architectures
- Sung Woo Chung, Hyong-Shik Kim, Chu Shik Jhon:
Distance-aware L2 Cache Organizations for Scalable Multiprocessor Systems. 24-32 - Ben H. H. Juurlink:
Unified Dual Data Caches. 33-40 - Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Ismail Kadayif:
CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors. 41-49
Synthesis (HL, LS, PS)
- Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Ahsan Raja Chowdhury, Syed Mostahed Ali Chowdhury:
Reversible Logic Synthesis for Minimization of Full-Adder Circuit. 50-54 - Loïc Pontani, Denis Dupont:
Scheduling and Assignment for Real-time Embedded Systems with Resource Contention. 55-61 - Nina Yevtushenko, Svetlana Zharikova, Maria Vetrova:
Multi Component Digital Circuit Optimization by Solving FSM Equations. 62-69
Processor and Memory Architectures
- P. Srivatsan, P. B. Sudarshan, P. P. Bhaskaran:
DYNORA: A New Caching Technique. 70-75 - Ahmet Akkas, Michael J. Schulte:
A Quadruple Precision and Dual Double Precision Floating-Point Multiplier. 76-81 - Rainer Schaffer, Renate Merker, Francky Catthoor:
Causality Constraints for Processor Architectures with Sub-Word Parallelism. 82-89 - Marc Bertola, Guy Bois:
A methodology for the design of AHB bus master wrappers. 90-97
Synthesis (HL, LS, PS)
- Winthir Brunnbauer, Thomas Wild, Jürgen Foag, Nuria Pazos:
A Constructive Algorithm with Look-Ahead for Mapping and Scheduling of Task Graphs with Conditional Edges. 98-103 - Mariusz Rawski, Henry Selvaraj, Tadeusz Luba:
An Application of Functional Decomposition in ROM-Based FSM Implementation in FPGA Devices. 104-111
Processor and Memory Architectures
- James E. Stine, Oliver M. Duverne:
Variations on Truncated Multiplication. 112-119 - Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar:
Exploring Storage Organization in ASIP Synthesis. 120-127 - Ricardo Chaves, Leonel Sousa:
RDSP: A RISC DSP based on Residue Number System. 128-137
Synthesis (HL, LS, PS)
- Gregorio Cappuccino:
Operating Region Modelling of Deep-submicron CMOS Buffers Driving Global Scope Inductive Interconnects. 138-143 - Ling Wang, Henry Selvaraj:
A Scheduling and Partitioning Scheme for Low Power Circuit Operating at Multiple Voltages. 144-147 - Lech Józwiak, Szymon Bieganski, Artur Chojnacki:
Information-driven Library-based Circuit Synthesis. 148-157
Special Architectures
- Peter Petrov, Alex Orailoglu:
Low-power Branch Target Buffer for Application-Specific Embedded Processors. 158-165 - Philip K. F. Hölzenspies, Erik Schepers, Wouter Bach, Mischa Jonker, Bart Sikkes, Gerard J. M. Smit, Paul J. M. Havinga:
A Communication Model Based on an n-Dimensional Torus Architecture Using Deadlock-Free Wormhole Routing. 166-172 - Marco Bera, Giovanni Danese, Ivo De Lotto, Francesco Leporati, Alvaro Spelgatti:
A Development and Simulation Environment for a Floating Point Operations FPGA Based Accelerator. 173-179 - Tang Lei, Shashi Kumar:
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture. 180-189
System-on-a-Chip
- Stephan Klaus, Sorin A. Huss:
A Novel Specification Model for IP-based Design. 190-196 - George Kornaros, Theofanis Orphanoudakis, Nicholaos Zervos:
An Efficient Implementation of Fair Load Balancing over Multi-CPU SOC Architectures. 197-205
Special Architectures
- Seetharaman Ramachandran, S. Srinivasan:
Design and FPGA Implementation of a Video Scalar with on-chip reduced memory utilization. 206-213 - Yang Qu, Juha-Pekka Soininen:
Estimating the Utilization of Embedded FPGA Co-Processor. 214-221 - Valery Sklyarov, Iouliia Skliarova, Arnaldo S. R. Oliveira, António de Brito Ferrari:
A Dynamically Reconfigurable Accelerator for Operations over Boolean and Ternary Vectors. 222-229 - Mario Hilgemeier, Nicole Drechsler, Rolf Drechsler:
Fast Heuristics for the Edge Coloring of Large Graphs. 230-239
Synthesis (HL, LS, PS)
- Amirali Baniasadi:
Back-End Dynamic Resource Allocation Heuristics for Power-Aware High-Performance Clustered Architectures. 240-247 - Michal Pleban, Hubert Niewiadomski, Piotr Buciak, Henry Selvaraj, Piotr Sapiecha, Tadeusz Luba:
NOAH, a tool for argument reduction, serial and parallel decomposition of decision tables. 248-254 - Valery Sklyarov, Iouliia Skliarova, Pedro Almeida, Manuel Almeida:
Design Tools and Reusable Libraries for FPGA-Based Digital Circuits. 255-263 - Karthikeyan Bhasyam, Kia Bazargan:
HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming. 264-271 - Fatih Kocan:
Reconfigurable Randomized K-way Graph Partitioning. 272-278 - Bharath Radhakrishnan, Muthukumar Venkatesan:
Multiple Voltage and Frequency Scheduling for Power Minimization. 279-285
Special Architectures
- Chichyang Chen, Rui-Lin Chen, Ming-Hwa Sheu:
A Fast Additive Normalization Method for Exponential Computation. 286-293 - Mark G. Arnold:
A VLIW Architecture for Logarithmic Arithmetic. 294-303
System-on-a-Chip (2) and Validation/Verification
- Richard Ruzicka:
Testable Design Verification Using Petri Nets. 304-311 - Ozgur Sinanoglu, Alex Orailoglu:
Hierarchical Constraint Conscious RT-level Test Generation. 312-318 - Goran Panic, Daniel Dietterle, Zoran Stamenkovic, Klaus Tittelbach-Helmrich:
A System-on-Chip Implementation of the IEEE 802.11a MAC Layer. 319-324 - Behzad Akbarpour, Sofiène Tahar:
The Application of Formal Verification to SPW Designs. 325-333
Applications of (Embedded) Digital Systems
- Filip Traugott, Kim Andersson, Andreas Löfgren, Lennart Lindh:
Successful Prototyping of a Real-Time Hardware Based Terrain Navigation Correlator Algorithm. 334-337 - Margarita Amor, Montserrat Bóo, Ángel del Río, Michael Wand, Wolfgang Straßer:
A New Algorithm for High-Speed Projection in Point Rendering Applications. 338-345 - Marco De Marinis, Luca Fanucci, A. Giambastiani, Alessandro Renieri, Alessandro Rocchi, Christian Rosadini, Claudio Sicilia, Daniele Sicilia:
Sensor Platform Design for Automotive Applications. 346-355
Specification and Modeling
- Raquel Fernández-Ramos, Jorge Romero-Sánchez, Francisco J. Ríos-Gómez, José F. Martín-Canales:
Modelling and Simulation of a Digital IC System Using SimulPet: Application to a Speech Coding Communication IC. 356-361 - Sandro Neves Soares, Flávio Rech Wagner:
T&D-Bench+ - A Software Environment for Modeling and Simulation of State-of-the-Art Processors. DSD 2003: 362-369 - Vladimir Hahanov, Raimund Ubar, Stanley Hyduke:
Back-Traced Deductive-Parallel Fault Simulation for Digital Systems. 370-377 - Adam Golda, Andrzej Kos:
Temperature Influence on Power Consumption and Time Delay. 378-383
Applications of (Embedded) Digital Systems
- Oguz Benderli, Yusuf Çagatay Tekmen, A. Neslin Ismailoglu:
A Real Time, Low Latency, FPGA Implementation of the 2-D Discrete Wavelet Transformation for Streaming Image Applications. 384-391
Applications of (Embedded) Digital Systems
- Om Prakash Gangwal, Johan G. W. M. Janssen, Selliah Rathnam, Erwin B. Bellers, Marc Duranton:
Understanding Video Pixel Processing Applications for Flexible Implementations. 392-401 - Nizamettin Aydin, Tughrul Arslan, David R. S. Cumming:
Power/Area Analysis and Optimization of a DS-SS receiver for an Integrated Sensor Microsystem. 402-407
Specification and Modeling
- Masanori Muroyama, Akihiko Hyodo, Takanori Okuma, Hiroto Yasuura:
A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits. 408-415 - Armin Wellig, Julien Zory:
Framed Complexity Analysis in SystemC for Multi-level Design Space Exploration. 416-425
Poster Papers
- S. T. G. S. Ramakrishna, H. S. Jamadagni:
Analytical Bounds on the Threads in IXP1200 Network Processor. 426-429 - Gregor Papa, Jurij Silc:
Concurrent Operation Scheduling and Unit Allocation with an Evolutionary Technique. 430-433 - Juan Manuel García Chamizo, Jerónimo Mora Pascual, Higinio Mora Mora:
Exact Numerical Processing. 434-437 - Nadia Nedjah, Luiza de Macedo Mourelle:
Stochastic Reconfigurable Hardware for Neural Networks. 438-442 - Radoslaw Czarnecki, Stanislaw Deniziak, Krzysztof Sapiecha:
An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs. 443-446 - Jouni Riihimäki, Väinö Helminen, Kimmo Kuusilinna, Timo D. Hämäläinen:
Distributing SoC Simulations over a Network of Computers. 447-450 - Petr Fiser, Jan Hlavicka, Hana Kubátová:
FC-Min: A Fast Multi-Output Boolean Minimizer. 451-454 - Václav Dvorák, Vladimír Kutálek:
A Methodology for Designing Communication Architectures for Multiprocessor SoCs. 455-458 - Guilin Chen, Guangyu Chen, Ismail Kadayif, Wei Zhang, Mahmut T. Kandemir, Ibrahim Kolcu, Ugur Sezer:
Compiler-Directed Management of Instruction Accesses. 459-462 - Zdenek Kotásek, Daniel Mika, Josef Strnadel:
Test scheduling for embedded systems. 463-467
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