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ORCIDMicroprocessors and Microsystems, Volume 30
Volume 30, Number 1, February 2006
- T. K. Priya, K. Sridharan:
A parallel algorithm, architecture and FPGA realization for high speed determination of the complete visibility graph for convex objects. 1-14 - Taskin Koçak, Jacob Engel:
A high throughput 3D-bus interconnect for network processors. 15-25 - A. Jameel, Mohammed Yakoob Siyal, N. Ikram:
A robust secure speech communication system using ITU-T G.723.1 and TMS320C6711 DSP. 26-32 - Sukwon Choi, Hojung Cha, Rhan Ha:
A selective DVS technique based on battery residual. 33-42 - Fernando J. Álvarez
, Álvaro Hernández, Jesús Ureña, Manuel Mazo, Juan Jesús García, José Antonio Jiménez, Ana Jiménez:
Real-time implementation of an efficient correlator for complementary sets of four sequences appl to ultrasonic pulse compression systems. 43-51 - Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi:
An integrated temporal partitioning and physical design framework for static compilation of reconfigurable computing systems. 52-62
Volume 30, Number 2, March 2006
- Slobodan Bojanic, Gabriel Caffarena, Slobodan Petrovic, Octavio Nieto-Taladriz:
FPGA for pseudorandom generator cryptanalysis. 63-71 - Zoran A. Salcic, Dong Hui, Partha S. Roop, Morteza Biglari-Abhari:
HiDRA - A reactive multiprocessor architecture for heterogeneous embedded systems. 72-85 - Bing-Chang Lai, Phillip J. McKerrow, Jo Abrantes:
The abstract vector processor. 86-101 - Kai-Feng Wang, Zhenzhou Ji, Ming-Zeng Hu:
Simultaneous multithreading trace processors: Improving trace processors performance. 102-116 - Dimitri Kagaris, Rajesh Aakuthota, Anila Verma:
Maximum sequence test pattern generators with irreducible characteristic polynomials. 117-123
Volume 30, Number 3, May 2006
- Darrin M. Hanna, Richard E. Haskell:
Flowpaths: Compiling stack-based IR to hardware. 125-136 - Sung Woo Chung, Gi-Ho Park, Hyo-Joong Suh, Han-Jong Kim, Jung-Bin Im, Jung-Wook Park, Sung-Bae Park:
Sim-ARM1136: A case study on the accuracy of the cycle-accurate simulator. 137-144 - Hyunsuk Moon, Reza Sedaghat:
FPGA-Based adaptive digital predistortion for radio-over-fiber links. 145-154 - Meng Yuan, Tan Lee, P. C. Ching, Yu Zhu:
Speech recognition on DSP: issues on computational efficiency and performance analysis. 155-164 - Xiaofan Yang, Graham M. Megson, David J. Evans:
Pancyclicity of Möbius cubes with faulty nodes. 165-172
Volume 30, Number 4, June 2006
- Qingfeng Zhuge, Chun Xue, Zili Shao, Meilin Liu, Meikang Qiu, Edwin Hsing-Mean Sha:
Design optimization and space minimization considering timing and code size via retiming and unfolding. 173-183 - K. M. M. Prabhu, G. Ghurumuruhan:
Transform decomposition method of pruning the FHT algorithms. 184-188 - Tao Li, Lizy Kurian John:
Operating system power minimization through run-time processor resource adaptation. 189-198 - M. Reza Javaheri, Reza Sedaghat, Leo Kant, Jason Zalev:
Verification and fault synthesis algorithm at switch-level. 199-208 - Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim:
A deterministic way-prediction scheme using power-aware replacement policy. 209-215 - Rajkiran Gottumukkal, Hau T. Ngo, Vijayan K. Asari:
Multi-lane architecture for eigenface based real-time face recognition. 216-224
Volume 30, Number 5, August 2006
- Kai-Feng Wang, Zhenzhou Ji, Ming-Zeng Hu:
Boosting SMT trace processors performance with data cache misssensitive thread scheduling mechanism. 225-233 - W. Kurdthongmee:
The hardware-based implementation of the colour palette generation stage of a colour image quantization algorithm. 234-249 - Joaquín Olivares, Javier Hormigo, Julio Villalba, Ignacio Benavides, Emilio L. Zapata:
SAD computation based on online arithmetic for motion estimation. 250-258 - Yongqiang Ye, Danwei Wang:
Implementation of ILC batch update using a robotic experimental setup. 259-267 - Cheol Hong Kim, Sung Woo Chung, Chu Shik Jhon:
PP-cache: A partitioned power-aware instruction cache architecture. 268-279
Volume 30, Number 6, September 2006
- J. Morris Chang, C. Dan Lo:
FPGA-based reconfigurable computing. 281-282
- Khaled Benkrid, Samir Belkacemi, Abdsamad Benkrid:
HIDE: A hardware intelligent description environment. 283-300 - André DeHon, Randy Huang, John Wawrzynek:
Stochastic spatial routing for reconfigurable networks. 301-318 - Ron Sass, Brian Greskamp, Brian Leonard, Jeff Young, Srinivas Beeravolu:
Online architectures: A theoretical formulation and experimental prototype. 319-333 - André DeHon, Yury Markovsky, Eylon Caspi, Michael Chu, Randy Huang, Stylianos Perissakis, Laura Pozzi, Joseph Yeh, John Wawrzynek:
Stream computations organized for reconfigurable execution. 334-354 - Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke:
Rapid generation of custom instructions using predefined dataflow structures. 355-366 - Jean-Philippe Diguet, Guy Gogniat, Jean Luc Philippe, Yannick Le Moullec, Sébastien Bilavarn, Christian Gamrat, Karim Ben Chehida, Michel Auguin, Xavier Fornari, Philippe Kajfasz:
EPICURE: A partitioning and co-design framework for reconfigurable computing. 367-387 - Jacob A. Bower, Wayne Luk, Oskar Mencer, Michael J. Flynn, Martin Morf:
Dynamic clock-frequencies for FPGAs. 388-397 - Muhammad Omer Cheema, Omar Hammami:
Application-specific SIMD synthesis for reconfigurable architectures. 398-412
Volume 30, Number 7, November 2006
- T. K. Priya, P. Rajesh Kumar, K. Sridharan:
A hardware-efficient scheme and FPGA realization for computation of single pair shortest path for a mobile automaton. 413-424 - Chin-Hsiung Wu, Shi-Jinn Horng, Yuh-Rau Wang, Horng-Ren Tsai:
Optimal geometric algorithms for digitized images on arrays with reconfigurable optical buses. 425-434 - Eva M. Ortigosa, Antonio Cañas, Eduardo Ros, Pilar Martínez Ortigosa, Sonia Mota, Javier Díaz:
Hardware description of multi-layer perceptrons with different abstraction levels. 435-444 - Joshua M. Lucas, Raymond Hoare, Ivan S. Kourtev, Alex K. Jones:
Technology mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). 445-456 - Yehuda Sadeh Weinraub, Shlomo Weiss:
Power-aware out-of-order issue logic in high-performance microprocessors. 457-467
Volume 30, Number 8, December 2006
- Yiyu Tan, Lo Wan Yiu, Chihang Yau, Richard Li, Anthony S. Fong:
A Java processor with hardware-support object-oriented instructions. 469-479 - A. Bradley, P. D. Noakes, Martin Fleury:
Design of an ultrasonic interface for a graphics tablet. 480-496 - Inmaculada Plaza, Carlos Medrano, Alfonso Blesa:
Analysis and implementation of the IEC 61131-3 software model under POSIX Real-Time operating systems. 497-508
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