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ORCIDMalgorzata Marek-Sadowska
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- affiliation: University of California, Santa Barbara, USA
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2020 – today
- 2023
[c171]Malgorzata Marek-Sadowska
:
ISPD 2023 Lifetime Achievement Award Bio. ISPD 2023: 265
2010 – 2019
- 2019
- [c170]Ali Abbasinasab, Malgorzata Marek-Sadowska:
Non-Uniform Temperature Distribution in Interconnects and Its Impact on Electromigration. ACM Great Lakes Symposium on VLSI 2019: 117-122 - 2018
- [j71]Ping-Lin Yang, Malgorzata Marek-Sadowska:
High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 26(7): 1209-1222 (2018) - [c169]Ali Abbasinasab, Malgorzata Marek-Sadowska:
RAIN: a tool for reliability assessment of interconnect networks - physics to software. DAC 2018: 133:1-133:6 - 2016
- [j70]Zhong Guan, Malgorzata Marek-Sadowska:
Incorporating Process Variations Into SRAM Electromigration Reliability Assessment Using Atomic Flux Divergence. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2195-2207 (2016) - [c168]Ping-Lin Yang, Malgorzata Marek-Sadowska:
Making split-fabrication more secure. ICCAD 2016: 91 - [c167]Zhong Guan, Malgorzata Marek-Sadowska:
An efficient and accurate algorithm for computing RC current response with applications to EM reliability evaluation. ICCAD 2016: 112 - [c166]Ping-Lin Yang, Malgorzata Marek-Sadowska:
A fast, fully verifiable, and hardware predictable ASIC design methodology. ICCD 2016: 364-367 - [c165]Zhong Guan, Malgorzata Marek-Sadowska:
AFD-based method for signal line EM reliability evaluation. ISQED 2016: 443-449 - 2015
- [j69]Di-An Li, Malgorzata Marek-Sadowska, Sani R. Nassif:
A Method for Improving Power Grid Resilience to Electromigration-Caused via Failures. IEEE Trans. Very Large Scale Integr. Syst. 23(1): 118-130 (2015) - [j68]Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech P. Maly:
Three-Dimensional Chips Can Be Cool: Thermal Study of VeSFET-Based 3-D Chips. IEEE Trans. Very Large Scale Integr. Syst. 23(5): 869-878 (2015) - [j67]Di-An Li, Malgorzata Marek-Sadowska, Sani R. Nassif:
T-VEMA: A Temperature- and Variation-Aware Electromigration Power Grid Analysis Tool. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2327-2331 (2015) - [c164]Li-C. Wang, Malgorzata Marek-Sadowska:
Machine Learning in Simulation-Based Analysis. ISPD 2015: 57-64 - [c163]Ali Abbasinasab, Malgorzata Marek-Sadowska:
Blech Effect in Interconnects: Applications and Design Guidelines. ISPD 2015: 111-118 - 2014
- [j66]Vivek S. Nandakumar, Malgorzata Marek-Sadowska:
On Optimal Kernel Size for Integrated CPU-GPUs - A Case Study. IEEE Comput. Archit. Lett. 13(2): 81-84 (2014) - [j65]Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech P. Maly:
Characterizing VeSFET-Based ICs With CMOS-Oriented EDA Infrastructure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4): 495-506 (2014) - [c162]Vivek S. Nandakumar, Malgorzata Marek-Sadowska:
System-Level Floorplan-Aware Analysis of Integrated CPU-GPUs. DAC 2014: 137:1-137:6 - [c161]Zhong Guan, Malgorzata Marek-Sadowska, Sani R. Nassif:
Statistical analysis of process variation induced SRAM electromigration degradation. ISQED 2014: 700-707 - [c160]Di-An Li, Malgorzata Marek-Sadowska:
Estimating true worst currents for power grid electromigration analysis. ISQED 2014: 708-714 - 2013
- [j64]Xiang Qiu, Malgorzata Marek-Sadowska:
Routing Challenges for Designs With Super High Pin Density. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(9): 1357-1368 (2013) - [c159]Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly:
Designing VeSFET-based ICs with CMOS-oriented EDA infrastructure. ISPD 2013: 130-136 - [c158]Zhong Guan, Malgorzata Marek-Sadowska, Sani R. Nassif:
SRAM bit-line electromigration mechanism and its prevention scheme. ISQED 2013: 286-293 - 2012
- [j63]Vivek S. Nandakumar, Malgorzata Marek-Sadowska:
A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 266-277 (2012) - [c157]Xiang Qiu, Malgorzata Marek-Sadowska:
Can pin access limit the footprint scaling? DAC 2012: 1100-1106 - [c156]Jen-Yi Wuu, Mark Simmons, Malgorzata Marek-Sadowska:
Post-placement lithographic hotspot detection and removal in one-dimensional gridded designs. ISQED 2012: 193-199 - [c155]Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly:
Vertical Slit Field Effect Transistor in ultra-low power applications. ISQED 2012: 384-390 - 2011
- [j62]Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly:
On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 229-241 (2011) - [j61]Aida Todri, Malgorzata Marek-Sadowska:
Reliability Analysis and Optimization of Power-Gated ICs. IEEE Trans. Very Large Scale Integr. Syst. 19(3): 457-468 (2011) - [j60]Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Performance Optimization Using Variable-Latency Design Style. IEEE Trans. Very Large Scale Integr. Syst. 19(10): 1874-1883 (2011) - [j59]Aida Todri, Malgorzata Marek-Sadowska:
Power Delivery for Multicore Systems. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2243-2255 (2011) - [c154]Jen-Yi Wuu, Fedor G. Pikus, Andres J. Torres, Malgorzata Marek-Sadowska:
Rapid layout pattern classification. ASP-DAC 2011: 781-786 - [c153]Vivek S. Nandakumar, Malgorzata Marek-Sadowska:
Layout effects in fine grain 3D integrated regular microprocessor blocks. DAC 2011: 639-644 - [c152]Di-An Li, Malgorzata Marek-Sadowska:
Variation-aware electromigration analysis of power/ground networks. ICCAD 2011: 571-576 - [c151]Vivek S. Nandakumar, Malgorzata Marek-Sadowska:
Low power, high throughput network-on-chip fabric for 3D multicore processors. ICCD 2011: 453-454 - [c150]Malgorzata Marek-Sadowska:
On old and new routing problems. ISPD 2011: 13-20 - [c149]Jen-Yi Wuu, Fedor G. Pikus, Malgorzata Marek-Sadowska:
Metrics for characterizing machine learning-based hotspot detection methods. ISQED 2011: 116-121 - 2010
- [j58]Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly:
Layout Generator for Transistor-Level High-Density Regular Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 197-210 (2010) - [c148]Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly:
Performance study of VeSFET-based, high-density regular circuits. ISPD 2010: 161-168 - [c147]Vivek S. Nandakumar, David Newmark, Yaping Zhan, Malgorzata Marek-Sadowska:
Statistical static timing analysis flow for transistor level macros in a microprocessor. ISQED 2010: 163-170 - [c146]Di-An Li, Malgorzata Marek-Sadowska, Bill Lee:
On-chip em-sensitive interconnect structures. SLIP 2010: 43-50
2000 – 2009
- 2009
- [j57]Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Timing-Aware Multiple-Delay-Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2): 245-258 (2009) - [j56]Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Spare Cells With Constant Insertion for Engineering Change. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 456-460 (2009) - [c145]Aida Todri, Malgorzata Marek-Sadowska:
Electromigration study of power-gated grids. ISLPED 2009: 315-318 - [c144]Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly:
Transistor-level layout of high-density regular circuits. ISPD 2009: 83-90 - [c143]Aida Todri, Malgorzata Marek-Sadowska, Francois Maire, Christophe Matheron:
A study of decoupling capacitor effectiveness in power and ground grid networks. ISQED 2009: 653-658 - 2008
- [j55]Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Improving the Resolution of Single-Delay-Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(5): 932-945 (2008) - [c142]Hailin Jiang, Malgorzata Marek-Sadowska:
Power gating scheduling for power/ground noise reduction. DAC 2008: 980-985 - [c141]Aida Todri, Malgorzata Marek-Sadowska, Joseph N. Kozhaya:
Power supply noise aware workload assignment for multi-core systems. ICCAD 2008: 330-337 - [c140]Aida Todri, Malgorzata Marek-Sadowska:
A study of reliability issues in clock distribution networks. ICCD 2008: 101-106 - [c139]Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Timing analysis considering IR drop waveforms in power gating designs. ICCD 2008: 532-537 - [c138]Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly, Andrzej Pfitzner, Dominik Kasprowicz:
Is there always performance overhead for regular fabric? ICCD 2008: 557-562 - [c137]Nilesh Modi, Malgorzata Marek-Sadowska:
ECO-Map: Technology remapping for post-mask ECO using simulated annealing. ICCD 2008: 652-657 - [c136]Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Timing-Aware Multiple-Delay-Fault Diagnosis. ISQED 2008: 246-253 - 2007
- [j54]Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Timing-Aware Power-Noise Reduction in Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 527-541 (2007) - [c135]Wojciech Maly, Yi-Wei Lin, Malgorzata Marek-Sadowska:
OPC-Free and Minimally Irregular IC Design Style. DAC 2007: 954-957 - [c134]Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
An Efficient Mechanism for Performance Optimization of Variable-Latency Designs. DAC 2007: 976-981 - [c133]Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Engineering change using spare cells with constant insertion. ICCAD 2007: 544-547 - [c132]Aida Todri, Malgorzata Marek-Sadowska, Shih-Chieh Chang:
Analysis and optimization of power-gated ICs with multiple power gating configurations. ICCAD 2007: 783-790 - [c131]Aida Todri, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Electromigration and voltage drop aware power grid optimization for power gated ICs. ISLPED 2007: 391-394 - [c130]Hailin Jiang, Malgorzata Marek-Sadowska:
Power-Gating Aware Floorplanning. ISQED 2007: 853-860 - [p2]Bo Hu, Malgorzata Marek-Sadowska:
mFAR: Multilevel Fixed-Points Addition-Based VLSI Placement. Modern Circuit Placement 2007: 229-245 - 2006
- [j53]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Analysis and methodology for multiple-fault diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 558-575 (2006) - [j52]Qinghua Liu, Malgorzata Marek-Sadowska:
Semi-Individual Wire-Length Prediction With Application to Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4): 611-624 (2006) - [j51]Yajun Ran, Malgorzata Marek-Sadowska:
Designing via-configurable logic blocks for regular fabric. IEEE Trans. Very Large Scale Integr. Syst. 14(1): 1-14 (2006) - [j50]Yajun Ran, Malgorzata Marek-Sadowska:
Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics. IEEE Trans. Very Large Scale Integr. Syst. 14(9): 998-1009 (2006) - [c129]Hailin Jiang, Malgorzata Marek-Sadowska:
Power/ground supply network optimization for power-gating. ICCD 2006: 332-337 - [c128]Vishal J. Mehta, Malgorzata Marek-Sadowska, Zhiyuan Wang, Kun-Han Tsai, Janusz Rajski:
Delay Fault Diagnosis for Non-Robust Test. ISQED 2006: 463-472 - [c127]Chung-Kuan Tsai, Malgorzata Marek-Sadowska:
Analysis of Process Variation's Effect on SRAM's Read Stability. ISQED 2006: 603-610 - [c126]Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology. ITC 2006: 1-10 - 2005
- [j49]Kai Wang, Malgorzata Marek-Sadowska:
On-chip power-supply network optimization using multigrid-based technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(3): 407-417 (2005) - [j48]Qinghua Liu, Malgorzata Marek-Sadowska:
A study of netlist structure and placement efficiency. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(5): 762-772 (2005) - [j47]Kai Wang, Yajun Ran, Hailin Jiang, Malgorzata Marek-Sadowska:
General skew constrained clock network sizing based on sequential linear programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(5): 773-782 (2005) - [j46]Bo Hu, Malgorzata Marek-Sadowska:
Multilevel fixed-point-addition-based VLSI placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(8): 1188-1203 (2005) - [j45]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Delay-fault diagnosis using timing information. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9): 1315-1325 (2005) - [j44]Yajun Ran, Alex Kondratyev, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska:
Eliminating false positives in crosstalk noise analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9): 1406-1419 (2005) - [c125]Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Skew-programmable clock design for FPGA and skew-aware placement. FPGA 2005: 33-40 - [c124]Hailin Jiang, Kai Wang, Malgorzata Marek-Sadowska:
Clock skew bounds estimation under power supply and process variations. ACM Great Lakes Symposium on VLSI 2005: 332-336 - [c123]Qinghua Liu, Malgorzata Marek-Sadowska:
A congestion-driven placement framework with local congestion prediction. ACM Great Lakes Symposium on VLSI 2005: 488-493 - [c122]Yajun Ran, Malgorzata Marek-Sadowska:
Via-configurable routing architectures and fast design mappability estimation for regular fabrics. ICCAD 2005: 25-32 - [c121]Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Timing-aware power noise reduction in layout. ICCAD 2005: 627-634 - [c120]Qinghua Liu, Malgorzata Marek-Sadowska:
Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement. ICCD 2005: 31-37 - [c119]Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif:
Benefits and Costs of Power-Gating Technique. ICCD 2005: 559-566 - [c118]Qinghua Liu, Malgorzata Marek-Sadowska:
Wire length prediction-based technology mapping and fanout optimization. ISPD 2005: 145-151 - [c117]Bo Hu, Yue Zeng, Malgorzata Marek-Sadowska:
mFAR: fixed-points-addition-based VLSI placement algorithm. ISPD 2005: 239-241 - [c116]Chung-Kuan Tsai, Malgorzata Marek-Sadowska:
An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis. ISQED 2005: 654-661 - 2004
- [j43]Luca Macchiarulo, Shih-Min Shu, Malgorzata Marek-Sadowska:
Pipelining Sequential Circuits with Wave Steering. IEEE Trans. Computers 53(9): 1205-1210 (2004) - [j42]Chih-Wei Jim Chang, Ming-Fu Hsiao, Bo Hu, Kai Wang, Malgorzata Marek-Sadowska, Chung-Kuan Cheng, Sao-Jie Chen:
Fast postplacement optimization using functional symmetries. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 102-118 (2004) - [j41]Bo Hu, Malgorzata Marek-Sadowska:
Fine granularity clustering-based placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 527-536 (2004) - [j40]Qinghua Liu, Bo Hu, Malgorzata Marek-Sadowska:
Individual wire-length prediction with application to timing-driven placement. IEEE Trans. Very Large Scale Integr. Syst. 12(10): 1004-1014 (2004) - [j39]Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Sequential delay budgeting with interconnect prediction. IEEE Trans. Very Large Scale Integr. Syst. 12(10): 1028-1037 (2004) - [c115]Yajun Ran, Malgorzata Marek-Sadowska:
Designing a via-configurable regular fabric. CICC 2004: 423-426 - [c114]Kai Wang, Malgorzata Marek-Sadowska:
Buffer sizing for clock power minimization subject to general skew constraints. DAC 2004: 159-164 - [c113]Yajun Ran, Malgorzata Marek-Sadowska:
On designing via-configurable cell blocks for regular fabrics. DAC 2004: 198-203 - [c112]Qinghua Liu, Malgorzata Marek-Sadowska:
Pre-layout wire length and congestion estimation. DAC 2004: 582-587 - [c111]Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Malgorzata Marek-Sadowska:
Eliminating False Positives in Crosstalk Noise Analysis. DATE 2004: 1192-1197 - [c110]Bo Hu, Malgorzata Marek-Sadowska:
Multilevel expansion-based VLSI placement with blockages. ICCAD 2004: 558-564 - [c109]Yajun Ran, Malgorzata Marek-Sadowska:
An integrated design flow for a via-configurable gate array. ICCAD 2004: 582-589 - [c108]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Diagnosis of Hold Time Defects. ICCD 2004: 192-199 - [c107]Kai Wang, Malgorzata Marek-Sadowska:
Potential Slack Budgeting with Clock Skew Optimization. ICCD 2004: 265-271 - [c106]Yajun Ran, Malgorzata Marek-Sadowska:
The Magic of a Via-Configurable Regular Fabric. ICCD 2004: 338-343 - [c105]Kai Wang, Malgorzata Marek-Sadowska:
Clock network sizing via sequential linear programming with time-domain analysis. ISPD 2004: 182-189 - [c104]Qinghua Liu, Malgorzata Marek-Sadowska:
A study of netlist structure and placement efficiency. ISPD 2004: 198-203 - [c103]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Delay Fault Diagnosis Using Timing Information. ISQED 2004: 485-490 - 2003
- [j38]Arindam Mukherjee, Malgorzata Marek-Sadowska:
Clock and Power Gating with Timing Closure. IEEE Des. Test Comput. 20(3): 32-39 (2003) - [j37]Chih-Wei Jim Chang, Ming-Fu Hsiao, Malgorzata Marek-Sadowska:
A new reasoning scheme for efficient redundancy addition and removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(7): 945-951 (2003) - [j36]Arindam Mukherjee, Malgorzata Marek-Sadowska:
Wave steering to integrate logic and physical syntheses. IEEE Trans. Very Large Scale Integr. Syst. 11(1): 105-120 (2003) - [j35]Amit Singh, Arindam Mukherjee, Luca Macchiarulo, Malgorzata Marek-Sadowska:
PITIA: an FPGA for throughput-intensive applications. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 354-363 (2003) - [j34]Lauren Hui Chen, Malgorzata Marek-Sadowska, Forrest Brewer:
Buffer delay change in the presence of power and ground noise. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 461-473 (2003) - [c102]Kai Wang, Malgorzata Marek-Sadowska:
On-chip power supply network optimization using multigrid-based technique. DAC 2003: 113-118 - [c101]Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Delay budgeting in sequential circuit with application on FPGA placement. DAC 2003: 202-207 - [c100]Bo Hu, Yosinori Watanabe, Alex Kondratyev, Malgorzata Marek-Sadowska:
Gain-based technology mapping for discrete-size cell libraries. DAC 2003: 574-579 - [c99]Bo Hu, Malgorzata Marek-Sadowska:
Wire length prediction based clustering and its application in placement. DAC 2003: 800-805 - [c98]Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska:
Temporofunctional crosstalk noise analysis. DAC 2003: 860-863 - [c97]Yajun Ran, Malgorzata Marek-Sadowska:
Crosstalk noise in FPGAs. DAC 2003: 944-949 - [c96]Kai Wang, Malgorzata Marek-Sadowska:
Power/Ground Mesh Area Optimization Using Multigrid-Based Technique. DATE 2003: 10850-10855 - [c95]Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Minimum-Area Sequential Budgeting for FPGA. ICCAD 2003: 813-817 - [c94]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Multiple Fault Diagnosis Using n-Detection Tests. ICCD 2003: 198- - [c93]Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen:
A crosstalk aware two-pin net router. ISCAS (5) 2003: 485-488 - [c92]Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen:
Minimizing coupling jitter by buffer resizing for coupled clock networks. ISCAS (5) 2003: 509-512 - [c91]Bo Hu, Malgorzata Marek-Sadowska:
Fine granularity clustering for large scale placement problems. ISPD 2003: 67-74 - [c90]Bo Hu, Hailin Jiang, Qinghua Liu, Malgorzata Marek-Sadowska:
Synthesis and placement flow for gain-based programmable regular fabrics. ISPD 2003: 197-203 - [c89]Chung-Kuan Tsai, Malgorzata Marek-Sadowska:
Modeling Crosstalk Induced Delay. ISQED 2003: 189-194 - [c88]Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen:
Minimizing Inter-Clock Coupling Jitter. ISQED 2003: 333-338 - [c87]Zhiyuan Wang, Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski:
An Efficient and Effective Methodology on the Multiple Fault Diagnosis. ITC 2003: 329-338 - [c86]Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Sequential delay budgeting with interconnect prediction. SLIP 2003: 23-30 - [c85]Qinghua Liu, Bo Hu, Malgorzata Marek-Sadowska:
Wire length prediction in constraint driven placement. SLIP 2003: 99-105 - 2002
- [j33]Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska:
Efficient circuit clustering for area and power reduction in FPGAs. ACM Trans. Design Autom. Electr. Syst. 7(4): 643-663 (2002) - [j32]Tong Xiao, Malgorzata Marek-Sadowska:
Using Temporal and Functional Information in Crosstalk Aware Static Timing Analysis. VLSI Design 15(3): 647-666 (2002) - [c84]Lauren Hui Chen, Malgorzata Marek-Sadowska, Forrest Brewer:
Coping with buffer delay change due to power and ground noise. DAC 2002: 860-865 - [c83]Arindam Mukherjee, Kai Wang, Lauren Hui Chen, Malgorzata Marek-Sadowska:
Sizing Power/Ground Meshes for Clocking and Computing Circuit Components. DATE 2002: 176-183 - [c82]Lauren Hui Chen, Malgorzata Marek-Sadowska:
Closed-Form Crosstalk Noise Metrics for Physical Design Applications. DATE 2002: 812-819 - [c81]Amit Singh, Malgorzata Marek-Sadowska:
Efficient circuit clustering for area and power reduction in FPGAs. FPGA 2002: 59-66 - [c80]Bo Hu, Malgorzata Marek-Sadowska:
Congestion minimization during placement without estimation. ICCAD 2002: 739-745 - [c79]Chih-Wei Jim Chang, Malgorzata Marek-Sadowska:
ATPG-based logic synthesis: an overview. ICCAD 2002: 786-789 - [c78]Lauren Hui Chen, Malgorzata Marek-Sadowska:
Incremental delay change due to crosstalk noise. ISPD 2002: 120-125 - [c77]Bo Hu, Malgorzata Marek-Sadowska:
FAR: fixed-points addition & relaxation based placement. ISPD 2002: 161-166 - [c76]Lauren Hui Chen, Malgorzata Marek-Sadowska:
Efficient Closed-Form Crosstalk Delay Metrics. ISQED 2002: 431-436 - [c75]Amit Singh, Malgorzata Marek-Sadowska:
FPGA interconnect planning. SLIP 2002: 23-30 - 2001
- [j31]Lauren Hui Chen, Malgorzata Marek-Sadowska:
Aggressor alignment for worst-case crosstalk noise. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(5): 612-621 (2001) - [c74]Chih-Wei Jim Chang, Kai Wang, Malgorzata Marek-Sadowska:
Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques. DAC 2001: 97-102 - [c73]Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska:
Latency and Latch Count Minimization in Wave Steered Circuits. DAC 2001: 383-388 - [c72]Tong Xiao, Malgorzata Marek-Sadowska:
Functional Correlation Analysis in Crosstalk Induced Critical Paths Identification. DAC 2001: 653-656 - [c71]Chih-Wei Jim Chang, Bo Hu, Malgorzata Marek-Sadowska:
In-place delay constrained power optimization using functional symmetries. DATE 2001: 377-382 - [c70]Nobuo Funabiki, Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska:
A Global Routing Technique for Wave-Steering Design Methodology. DSD 2001: 430-437 - [c69]Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska:
Interconnect pipelining in a throughput-intensive FPGA architecture. FPGA 2001: 153-160 - [c68]Chih-Wei Jim Chang, Malgorzata Marek-Sadowska:
Who are the alternative wires in your neighborhood? (alternative wires identification without search). ACM Great Lakes Symposium on VLSI 2001: 103-108 - [c67]Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska:
Interconnect Resource-Aware Placement for Hierarchical FPGAs. ICCAD 2001: 132-136 - [c66]Chih-Wei Jim Chang, Malgorzata Marek-Sadowska:
Single-Pass Redundancy Addition and Removal. ICCAD 2001: 606-609 - [c65]Tong Xiao, Malgorzata Marek-Sadowska:
Gate Sizing to Eliminate Crosstalk Induced Timing Violation. ICCD 2001: 186-191 - [c64]Ganapathy Parthasarathy, Malgorzata Marek-Sadowska, Arindam Mukherjee, Amit Singh:
Interconnect complexity-aware FPGA placement using Rent's rule. SLIP 2001: 115-121 - 2000
- [j30]Yu-Liang Wu, Hongbing Fan, Malgorzata Marek-Sadowska, C. K. Wong:
OBDD Minimization Based on Two-Level Representation of Boolean Functions. IEEE Trans. Computers 49(12): 1371-1379 (2000) - [j29]Kun-Han Tsai, Janusz Rajski, Malgorzata Marek-Sadowska:
Star test: the theory and its applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(9): 1052-1064 (2000) - [c63]Chih-Wei Jim Chang, Chung-Kuan Cheng, Peter Suaris, Malgorzata Marek-Sadowska:
Fast post-placement rewiring using easily detectable functional symmetries. DAC 2000: 286-289 - [c62]Luca Macchiarulo, Malgorzata Marek-Sadowska:
Wave-steering one-hot encoded FSMs. DAC 2000: 357-360 - [c61]Luca Macchiarulo, Shih-Ming Shu, Malgorzata Marek-Sadowska:
Wave Steered FSMs. DATE 2000: 270-276 - [c60]Amit Singh, Luca Macchiarulo, Arindam Mukherjee, Malgorzata Marek-Sadowska:
A novel high throughput reconfigurable FPGA architecture. FPGA 2000: 22-29 - [c59]Tong Xiao, Malgorzata Marek-Sadowska:
Worst Delay Estimation in Crosstalk Aware Static Timing Analysis. ICCD 2000: 115-120 - [c58]Lauren Hui Chen, Malgorzata Marek-Sadowska:
Aggressor alignment for worst-case coupling noise. ISPD 2000: 48-54 - [c57]Tong Xiao, Malgorzata Marek-Sadowska:
Efficient Delay Calculation in Presence of Crosstalk. ISQED 2000: 491-498
1990 – 1999
- 1999
- [j28]Douglas Chang, Malgorzata Marek-Sadowska:
Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs. IEEE Trans. Computers 48(6): 565-578 (1999) - [j27]Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska:
Circuit Optimization by Rewiring. IEEE Trans. Computers 48(9): 962-970 (1999) - [j26]Chih-Chang Lin, Kuang-Chien Chen, Malgorzata Marek-Sadowska:
Logic synthesis for engineering change. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(3): 282-292 (1999) - [j25]Ashok Vittal, Lauren Hui Chen, Malgorzata Marek-Sadowska, Kai-Ping Wang, Sherry Yang:
Crosstalk in VLSI interconnections. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(12): 1817-1824 (1999) - [c56]Tong Xiao, Malgorzata Marek-Sadowska:
Crosstalk Reduction by Transistor Sizing. ASP-DAC 1999: 137-140 - [c55]Arindam Mukherjee, Malgorzata Marek-Sadowska, Stephen I. Long:
Wave pipelining YADDs-a feasibility study. CICC 1999: 559-562 - [c54]Arindam Mukherjee, Ranganathan Sudhakar, Malgorzata Marek-Sadowska, Stephen I. Long:
Wave Steering in YADDs: A Novel Non-Iterative Synthesis and Layout Technique. DAC 1999: 466-471 - [c53]Amit Singh, Malgorzata Marek-Sadowska:
Circuit clustering using graph coloring. ISPD 1999: 164-169 - [c52]Kuo-Hui Tsai, Tompson, Janusz Rajski, Malgorzata Marek-Sadowska:
STAR-ATPG: a high speed test pattern generator for large scan designs. ITC 1999: 1021-1030 - [c51]Ashok Vittal, Lauren Hui Chen, Malgorzata Marek-Sadowska, Kai-Ping Wang, Sherry Yang:
Modeling Crosstalk in Resistive VLSI Interconnections. VLSI Design 1999: 470-475 - 1998
- [j24]David Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska:
A hybrid methodology for switching activities estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(4): 357-366 (1998) - [j23]Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee:
Test-point insertion: scan paths through functional logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(9): 838-851 (1998) - [j22]Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen:
Cost-free scan: a low-overhead scan path design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(9): 852-861 (1998) - [j21]Ashok Vittal, Malgorzata Marek-Sadowska:
Power Distribution Synthesis for VLSI. VLSI Design 7(1): 59-72 (1998) - [c50]Douglas Chang, Kwang-Ting Cheng, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee:
Functional Scan Chain Testing. DATE 1998: 278-283 - [c49]Douglas Chang, Malgorzata Marek-Sadowska:
Partitioning Sequential Circuits on Dynamically Reconfiguable FPGAs. FPGA 1998: 161-167 - 1997
- [j20]Chien-Chung Tsai, Malgorzata Marek-Sadowska:
Boolean Functions Classification via Fixed Polarity Reed-Muller Forms. IEEE Trans. Computers 46(2): 173-186 (1997) - [j19]Ashok Vittal, Malgorzata Marek-Sadowska:
Crosstalk reduction for VLSI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(3): 290-298 (1997) - [j18]Yu-Liang Wu, Malgorzata Marek-Sadowska:
Routing for array-type FPGA's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(5): 506-518 (1997) - [j17]Chih-Chang Lin, Malgorzata Marek-Sadowska:
On designing universal logic blocks and their application to FPGA design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(5): 519-527 (1997) - [j16]Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska:
Postlayout logic restructuring using alternative wires. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(6): 587-596 (1997) - [j15]Ashok Vittal, Malgorzata Marek-Sadowska:
Low-power buffered clock tree design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(9): 965-975 (1997) - [c48]Yu-Liang Wu, Douglas Chang, Malgorzata Marek-Sadowska, Shuji Tsukiyama:
Not necessarily more switches more routability [sic.]. ASP-DAC 1997: 579-584 - [c47]Douglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang-Ting Cheng:
A Test Synthesis Approach to Reducing BALLAST DFT Overhead. DAC 1997: 466-471 - [c46]Kun-Han Tsai, Sybille Hellebrand, Janusz Rajski, Malgorzata Marek-Sadowska:
STARBIST: Scan Autocorrelated Random Pattern Generation. DAC 1997: 472-477 - [c45]Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska:
Post-Layout Logic Restructuring for Performance Optimization. DAC 1997: 662-665 - [c44]Douglas Chang, Malgorzata Marek-Sadowska:
Buffer Minimization and Time-Multiplexed I/O on Dynamically Reconfigurable FPGAs. FPGA 1997: 142-148 - [c43]Marek A. Perkowski, Malgorzata Marek-Sadowska, Lech Józwiak, Tadeusz Luba, Stan Grygiel, Miroslawa Nowicka, Rahul Malvi, Zhi Wang, Jin S. Zhang:
Decomposition of Multiple-Valued Relations . ISMVL 1997: 13-18 - [c42]Stan Grygiel, Marek A. Perkowski, Malgorzata Marek-Sadowska, Tadeusz Luba, Lech Józwiak:
Cube Diagram Bundles: A New Representation of Strongly Unspecified Multiple-Valued Functions and Relations. ISMVL 1997: 287-292 - [c41]Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski:
Scan-Encoded Test Pattern Generation for BIST. ITC 1997: 548-556 - 1996
- [j14]Chien-Chung Tsai, Malgorzata Marek-Sadowska:
Generalized Reed-Muller Forms as a Tool to Detect Symmetries. IEEE Trans. Computers 45(1): 33-40 (1996) - [j13]Yu-Liang Wu, Shuji Tsukiyama, Malgorzata Marek-Sadowska:
Graph based analysis of 2-D FPGA routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(1): 33-44 (1996) - [j12]Shih-Chieh Chang, Malgorzata Marek-Sadowska, TingTing Hwang:
Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(10): 1226-1236 (1996) - [j11]Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng:
Perturb and simplify: multilevel Boolean network optimizer. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1494-1504 (1996) - [c40]Chien-Chung Tsai, Malgorzata Marek-Sadowska:
Multilevel Logic Synthesis for Arithmetic Functions. DAC 1996: 242-247 - [c39]Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee:
Test Point Insertion: Scan Paths through Combinational Logic. DAC 1996: 268-273 - [c38]David Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska:
A New Hybrid Methodology for Power Estimation. DAC 1996: 439-444 - [c37]Chih-Chang Lin, Malgorzata Marek-Sadowska, Kuang-Chien Chen, Mike Tien-Chien Lee:
Sequential Permissible Functions and their Application to Circuit Optimization. ED&TC 1996: 334-339 - [c36]Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Perturb and Simplify: Optimizing Combinational Circuits with External Don't Cares. ED&TC 1996: 402-406 - [c35]Chien-Chung Tsai, Malgorzata Marek-Sadowska:
Logic Synthesis for Testability. Great Lakes Symposium on VLSI 1996: 118-121 - [c34]Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska:
Fast Boolean optimization by rewiring. ICCAD 1996: 262-269 - [c33]Ashok Vittal, Hein Ha, Forrest Brewer, Malgorzata Marek-Sadowska:
Clock skew optimization for ground bounce control. ICCAD 1996: 395-399 - 1995
- [j10]Malgorzata Marek-Sadowska, Majid Sarrafzadeh:
The crossing distribution problem [IC layout]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(4): 423-433 (1995) - [c32]Chih-Chang Lin, David Ihsin Cheng, Malgorzata Marek-Sadowska, Kuang-Chien Chen:
Logic rectification and synthesis for engineering change. ASP-DAC 1995 - [c31]Yu-Liang Wu, Malgorzata Marek-Sadowska:
Routing on regular segmented 2-D FPGAs. ASP-DAC 1995 - [c30]Ashok Vittal, Malgorzata Marek-Sadowska:
Power Optimal Buffered Clock Tree Design. DAC 1995: 497-502 - [c29]Ashok Vittal, Malgorzata Marek-Sadowska:
Power Distribution Topology Design. DAC 1995: 503-507 - [c28]Yu-Liang Wu, Malgorzata Marek-Sadowska:
Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing. DAC 1995: 568-573 - [c27]Chih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng:
Logic Synthesis for Engineering Change. DAC 1995: 647-652 - [c26]Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng:
An Efficient Algorithm for Local Don't Care Sets Calculation. DAC 1995: 663-667 - [c25]Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen:
Cost-free scan: a low-overhead scan path design methodology. ICCAD 1995: 528-533 - [c24]David Ihsin Cheng, Chih-Chang Lin, Malgorzata Marek-Sadowska:
Circuit partitioning with logic perturbation. ICCAD 1995: 650-655 - 1994
- [j9]David Ihsin Cheng, Malgorzata Marek-Sadowska:
On the Verification of Function Equivalence with unknown Input Correspondence. J. Circuits Syst. Comput. 4(2): 223-242 (1994) - [c23]Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska:
Layout Driven Logic Synthesis for FPGAs. DAC 1994: 308-313 - [c22]Chien-Chung Tsai, Malgorzata Marek-Sadowska:
Boolean Matching Using Generalized Reed-Muller Forms. DAC 1994: 339-344 - [c21]Ashok Vittal, Malgorzata Marek-Sadowska:
Minimal Delay Interconnect Design Using Alphabetic Trees. DAC 1994: 392-396 - [c20]Yu-Liang Wu, Malgorzata Marek-Sadowska:
An Efficient Router for 2-D Field Programmable Gate Arrays. EDAC-ETC-EUROASIC 1994: 412-416 - [c19]Shih-Chieh Chang, David Ihsin Cheng, Malgorzata Marek-Sadowska:
Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions. EDAC-ETC-EUROASIC 1994: 620-624 - [c18]Yu-Liang Wu, Shuji Tsukiyama, Malgorzata Marek-Sadowska:
On computational complexity of a detailed routing problem in two dimensional FPGAs. Great Lakes Symposium on VLSI 1994: 70-75 - [c17]Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Perturb and simplify: multi-level boolean network optimizer. ICCAD 1994: 2-5 - [c16]Chih-Chang Lin, Malgorzata Marek-Sadowska, Duane Gatlin:
Universal logic gate for FPGA design. ICCAD 1994: 164-168 - [c15]Chien-Chung Tsai, Malgorzata Marek-Sadowska:
Detecting Symmetric Variables in Boolean Functions using Generalized Reel-Muller Forms. ISCAS 1994: 287-290 - 1993
- [j8]Shen Lin, Ernest S. Kuh, Malgorzata Marek-Sadowska:
Stepwise equivalent conductance circuit simulation technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(5): 672-683 (1993) - [c14]Yu-Liang Wu, Malgorzata Marek-Sadowska:
Graph based analysis of FPGA routing. EURO-DAC 1993: 104-109 - [c13]Chien-Chung Tsai, Malgorzata Marek-Sadowska:
Efficient minimization algorithms for fixed polarity AND/XOR canonical networks. Great Lakes Symposium on VLSI 1993: 76-79 - [p1]Malgorzata Marek-Sadowska:
Issues in Timing Driven Layout. Algorithmic Aspects of VLSI Layout 1993: 1-24 - 1992
- [j7]Malgorzata Marek-Sadowska:
Switch box routing: a retrospective. Integr. 13(1): 39-65 (1992) - [j6]Robi Dutta, Malgorzata Marek-Sadowska:
Algorithm for wire sizing of Power and Ground Networks in VLSI Designs. J. Circuits Syst. Comput. 2(2): 141-158 (1992) - [c12]Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Technology Mapping via Transformations of Function Graphs. ICCD 1992: 159-162 - [c11]Shen Lin, Ernest S. Kuh, Malgorzata Marek-Sadowska:
A New Accurate and Efficient Timing Simulator. VLSI Design 1992: 281-286 - 1991
- [c10]Shen Lin, Malgorzata Marek-Sadowska, Ernest S. Kuh:
SWEC: a Step Wise Equivalent Conductance timing simulator for CMOS VLSI circuits. EURO-DAC 1991: 142-148 - [c9]Shen Lin, Malgorzata Marek-Sadowska:
A fast and efficient algorithm for determining fanout trees in large networks. EURO-DAC 1991: 539-544 - [c8]Malgorzata Marek-Sadowska, Majid Sarrafzadeh:
The Crossing Distribution Problem. ICCAD 1991: 528-531 - 1990
- [c7]Shen Lin, Malgorzata Marek-Sadowska, Ernest S. Kuh:
Delay and Area Optimization in Standard-Cell Design. DAC 1990: 349-352 - [c6]Massoud Pedram, Malgorzata Marek-Sadowska, Ernest S. Kuh:
Floorplanning with Pin Assignment. ICCAD 1990: 98-101 - [c5]Malgorzata Marek-Sadowska, Shen P. Lin:
Pin assignment for improved performance in standard cell design. ICCD 1990: 339-342
1980 – 1989
- 1989
- [c4]Rajiv Dutta, Malgorzata Marek-Sadowska:
Automatic Sizing of Power/Ground (P/G) Networks in VLSI. DAC 1989: 783-786 - [c3]Malgorzata Marek-Sadowska, Shen Lin:
Timing driven placement. ICCAD 1989: 94-97 - [c2]Fillia Makedon, Malgorzata Marek-Sadowska:
Analysis of Heuristic Reasoning for the Visualization of CAD Quadratic. ICCAL 1989: 359-378 - 1987
- [j5]Malgorzata Marek-Sadowska:
Pad Assignment for Power Nets in VLSI Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(4): 550-560 (1987) - 1985
- [c1]Malgorzata Marek-Sadowska:
Two-dimensional router for double layer layout. DAC 1985: 117-123 - 1984
- [j4]Tom Tsan-Kuo Tarng, Malgorzata Marek-Sadowska, Ernest S. Kuh:
An Efficient Single-Row Routing Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3(3): 178-183 (1984) - [j3]Malgorzata Marek-Sadowska:
An Unconstrained Topological Via Minimization Problem for Two-Layer Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3(3): 184-190 (1984) - [j2]Jeong-Tyng Li, Malgorzata Marek-Sadowska:
Global Routing for Gate Array. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3(4): 298-307 (1984) - 1983
- [j1]Malgorzata Marek-Sadowska, Tom Tsan-Kuo Tarng:
Single-Layer Routing for VLSI: Analysis and Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2(4): 246-259 (1983)
Coauthor Index
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