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2020 – today
- 2024
[c130]Jan Lappas, Mohamed Amine Riahi, Christian Weis, Norbert Wehn, Sani R. Nassif:
Timing Analysis beyond Complementary CMOS Logic Styles. ASPDAC 2024: 189-194- [c129]Priyanjana Pal, Haibin Zhao, Maha Shatta, Michael Hefenbrock, Sina Bakhtavari Mamaghani, Sani R. Nassif, Michael Beigl, Mehdi B. Tahoori:
Analog Printed Spiking Neuromorphic Circuit. DATE 2024: 1-6 - [c128]Zhe Zhang, Christian Weis, Norbert Wehn, Mehdi B. Tahoori, Sani R. Nassif:
Do Radiation and Aging Impact DVFS? TCAD-based Analysis on 22 nm FDSOI Latches. IOLTS 2024: 1-6 - [c127]Philipp Fengler, Sani R. Nassif, Ulf Schlichtmann:
Toward Early Stage Dynamic Power Estimation: Exploring Alternative Machine Learning Methods and Simulation Schemes. ISQED 2024: 1-8 - [c126]Zhe Zhang, Mahta Mayahinia, Christian Weis, Norbert Wehn, Mehdi B. Tahoori, Sani R. Nassif, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian:
Addressing the Combined Effect of Transistor and Interconnect Aging in SRAM towards Silicon Lifecycle Management. VTS 2024: 1-5 - 2023
- [c125]Grégoire Eggermann, Marco Rios, Giovanni Ansaloni, Sani R. Nassif, David Atienza:
A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication. VLSI-SoC 2023: 1-6
2010 – 2019
- 2019
- [c124]Alexandra Listl, Daniel Mueller-Gritschneder
, Ulf Schlichtmann, Sani R. Nassif:
SRAM Design Exploration with Integrated Application-Aware Aging Analysis. DATE 2019: 1249-1252 - 2015
- [j28]Sani R. Nassif, Martin A. Trefzer:
Editorial. IET Comput. Digit. Tech. 9(4): 185-186 (2015) - [j27]Di-An Li, Malgorzata Marek-Sadowska, Sani R. Nassif:
A Method for Improving Power Grid Resilience to Electromigration-Caused via Failures. IEEE Trans. Very Large Scale Integr. Syst. 23(1): 118-130 (2015) - [j26]Di-An Li, Malgorzata Marek-Sadowska, Sani R. Nassif:
T-VEMA: A Temperature- and Variation-Aware Electromigration Power Grid Analysis Tool. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2327-2331 (2015) - [c123]Mohammad Saber Golanbari, Saman Kiamehr, Mehdi Baradaran Tahoori, Sani R. Nassif:
Analysis and optimization of flip-flops under process and runtime variations. ISQED 2015: 191-196 - 2014
- [j25]Andreas Herkersdorf, Hananeh Aliee, Michael Engel, Michael Glaß, Christina Gimmler-Dumont, Jörg Henkel, Veit Kleeberger, Michael A. Kochte, Johannes Maximilian Kühn, Daniel Mueller-Gritschneder, Sani R. Nassif, Holm Rauchfuss, Wolfgang Rosenstiel, Ulf Schlichtmann, Muhammad Shafique, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Christian Weis, Hans-Joachim Wunderlich:
Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience. Microelectron. Reliab. 54(6-7): 1066-1074 (2014) - [c122]Sani R. Nassif, Gi-Joon Nam, Jerry Hayes, Sani Fakhouri:
Applying VLSI EDA to energy distribution system design. ASP-DAC 2014: 91-96 - [c121]Saman Kiamehr, Thomas H. Osiecki, Mehdi Baradaran Tahoori, Sani R. Nassif:
Radiation-Induced Soft Error Analysis of SRAMs in SOI FinFET Technology: A Device to Circuit Approach. DAC 2014: 201:1-201:6 - [c120]Ulf Schlichtmann, Veit Kleeberger, Jacob A. Abraham, Adrian Evans, Christina Gimmler-Dumont, Michael Glaß, Andreas Herkersdorf, Sani R. Nassif, Norbert Wehn:
Connecting different worlds - Technology abstraction for reliability-aware design and Test. DATE 2014: 1-8 - [c119]Iris Hui-Ru Jiang, Gi-Joon Nam, Hua-Yu Chang, Sani R. Nassif, Jerry Hayes:
Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations. ICCAD 2014: 382-388 - [c118]Gi-Joon Nam, Sani R. Nassif:
Opportunities in power distribution network system optimization: from EDA perspective. ISPD 2014: 149-150 - [c117]Zhong Guan, Malgorzata Marek-Sadowska, Sani R. Nassif:
Statistical analysis of process variation induced SRAM electromigration degradation. ISQED 2014: 700-707 - 2013
- [j24]Veit Kleeberger, Christina Gimmler-Dumont, Christian Weis, Andreas Herkersdorf, Daniel Mueller-Gritschneder, Sani R. Nassif, Ulf Schlichtmann, Norbert Wehn:
A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience. IEEE Micro 33(4): 46-55 (2013) - [j23]Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars Liebmann, Puneet Gupta:
Layout Decomposition and Legalization for Double-Patterning Technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(2): 202-215 (2013) - [c116]Jörg Henkel, Lars Bauer, Nikil D. Dutt, Puneet Gupta, Sani R. Nassif, Muhammad Shafique, Mehdi Baradaran Tahoori, Norbert Wehn:
Reliable on-chip systems in the nano-era: lessons learnt and future trends. DAC 2013: 99:1-99:10 - [c115]Farshad Firouzi, Saman Kiamehr, Mehdi Baradaran Tahoori, Sani R. Nassif:
Incorporating the impacts of workload-dependent runtime variations into timing analysis. DATE 2013: 1022-1025 - [c114]Xingsheng Wang, Binjie Cheng, Andrew R. Brown, Campbell Millar, Jente B. Kuang, Sani R. Nassif, Asen Asenov:
Impact of statistical variability and charge trapping on 14 nm SOI FinFET SRAM cell stability. ESSDERC 2013: 234-237 - [c113]Yuma Higuchi, Kenichi Shinkai, Masanori Hashimoto, Rahul M. Rao, Sani R. Nassif:
Extracting device-parameter variations using a single sensitivity-configurable ring oscillator. ETS 2013: 1-6 - [c112]Thomas H. Osiecki, Min-Yu Tsai, Anne E. Gattiker, Damir A. Jamsek, Sani R. Nassif, William Evan Speight, Cliff C. N. Sze:
Hardware Acceleration of an Efficient and Accurate Proton Therapy Monte Carlo. ICCS 2013: 2241-2250 - [c111]Shayak Banerjee, Zhuo Li, Sani R. Nassif:
ICCAD-2013 CAD contest in mask optimization and benchmark suite. ICCAD 2013: 271-274 - [c110]Binjie Cheng, Xingsheng Wang, Andrew R. Brown, Jente B. Kuang, Dave Reid, Campbell Millar, Sani R. Nassif, Asen Asenov:
SRAM device and cell co-design considerations in a 14nm SOI FinFET technology. ISCAS 2013: 2339-2342 - [c109]Zhong Guan, Malgorzata Marek-Sadowska, Sani R. Nassif:
SRAM bit-line electromigration mechanism and its prevention scheme. ISQED 2013: 286-293 - [c108]Sani R. Nassif, Gi-Joon Nam, Shayak Banerjee:
Wire delay variability in nanoscale technology and its impact on physical design. ISQED 2013: 591-596 - [c107]Sani R. Nassif, Yale N. Patt, Magdy S. Abadir:
Keynote 1 - VLSI 2.0: R&D Post Moore. VLSI-SoC 2013 - 2012
- [j22]Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Gi-Joon Nam, Michael Orshansky, David Z. Pan:
An accurate sparse-matrix based framework for statistical static timing analysis. Integr. 45(4): 365-375 (2012) - [c106]Vijay Janapa Reddi, David Z. Pan, Sani R. Nassif, Keith A. Bowman:
Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues. ASP-DAC 2012: 7-16 - [c105]Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jerry Hayes, Sani R. Nassif:
Yield estimation via multi-cones. DAC 2012: 1107-1112 - [c104]Zhuo Li, Raju Balasubramanian, Frank Liu, Sani R. Nassif:
2012 TAU power grid simulation contest: Benchmark suite and results. ICCAD 2012: 643-646 - [c103]Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars W. Liebmann, Puneet Gupta:
O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction. ICICDT 2012: 1-4 - [c102]Shayak Banerjee, Kanak B. Agarwal, Sani R. Nassif:
Design-aware lithography. ISPD 2012: 3-8 - [c101]Eun Jung Jang, Anne Gattiker, Sani R. Nassif, Jacob A. Abraham:
An oscillation-based test structure for timing information extraction. VTS 2012: 74-79 - 2011
- [j21]Xiaoji Ye, Wei Dong, Peng Li, Sani R. Nassif:
Hierarchical Multialgorithm Parallel Circuit Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(1): 45-58 (2011) - [j20]Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif:
Simultaneous Layout Migration and Decomposition for Double Patterning Technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 284-294 (2011) - [j19]Jente B. Kuang, Jeremy D. Schaub, Fadi H. Gebara, Dieter F. Wendel, Thomas Fröhnel, Sudesh Saroop, Sani R. Nassif, Kevin J. Nowka:
The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(9): 2010-2016 (2011) - [j18]Yun Ye, Frank Liu, Min Chen, Sani R. Nassif, Yu Cao:
Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 987-996 (2011) - [j17]Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif:
The Impact of Statistical Leakage Models on Design Yield Estimation. VLSI Design 2011: 471903:1-471903:12 (2011) - [c100]Eun Jung Jang, Jaeyong Chung, Anne E. Gattiker, Sani R. Nassif, Jacob A. Abraham:
Post-Silicon Timing Validation Method Using Path Delay Measurements. Asian Test Symposium 2011: 232-237 - [c99]Shayak Banerjee, Kanak B. Agarwal, Sani R. Nassif:
Electrically-driven retargeting for nanoscale layouts. CICC 2011: 1-4 - [c98]Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars Liebmann, Puneet Gupta:
A framework for double patterning-enabled design. ICCAD 2011: 14-20 - [c97]Rouwaida Kanj, Tong Li, Rajiv V. Joshi, Kanak Agarwal, Ali Sadigh, David Winston, Sani R. Nassif:
Accelerated statistical simulation via on-demand Hermite spline interpolations. ICCAD 2011: 353-360 - [c96]Zhuo Li, Raju Balasubramanian, Frank Liu, Sani R. Nassif:
2011 TAU power grid simulation contest: Benchmark suite and results. ICCAD 2011: 478-481 - [c95]Mehrdad Majzoobi, Golsa Ghiaasi, Farinaz Koushanfar, Sani R. Nassif:
Ultra-low power current-based PUF. ISCAS 2011: 2071-2074 - [c94]Shayak Banerjee, Kanak B. Agarwal, Sani R. Nassif, James A. Culp, Lars Liebmann, Michael Orshansky:
Coupling timing objectives with optical proximity correction for improved timing yield. ISQED 2011: 97-102 - [c93]Eun Jung Jang, Anne E. Gattiker, Sani R. Nassif, Jacob A. Abraham:
Efficient and product-representative timing model validation. VTS 2011: 90-95 - 2010
- [j16]Sani R. Nassif:
'Tis the gift to be simple. IEEE Des. Test Comput. 27(2): 84-86 (2010) - [j15]Ritu Singhal, Asha Balijepalli, Anupama R. Subramaniam, Chi-Chao Wang, Frank Liu, Sani R. Nassif, Yu Cao:
Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation. IEEE Trans. Very Large Scale Integr. Syst. 18(4): 666-670 (2010) - [c92]Sani R. Nassif:
The light at the end of the CMOS tunnel. ASAP 2010: 4-9 - [c91]Jente B. Kuang, Jeremy D. Schaub, Fadi H. Gebara, Dieter F. Wendel, Sudesh Saroop, Tuyet Nguyen, Thomas Fröhnel, Antje Müller, Christopher M. Durham, Rolf Sautter, Bryan Lloyd, Bryan J. Robbins, Juergen Pille, Sani R. Nassif, Kevin J. Nowka:
A 32nm 0.5V-supply dual-read 6T SRAM. CICC 2010: 1-4 - [c90]Sani R. Nassif, Nikil Mehta, Yu Cao:
A resilience roadmap. DATE 2010: 1011-1016 - [c89]Shayak Banerjee, Kanak B. Agarwal, Chin Ngai Sze, Sani R. Nassif, Michael Orshansky:
A methodology for propagating design tolerances to shape tolerances for use in manufacturing. DATE 2010: 1273-1278 - [c88]Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif:
Template-mask design methodology for double patterning technology. ICCAD 2010: 107-111 - [c87]Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif:
Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives. ISLPED 2010: 337-342 - [c86]Sani R. Nassif, Kevin J. Nowka:
Physical design challenges beyond the 22nm node. ISPD 2010: 13-14
2000 – 2009
- 2009
- [c85]Sherief Reda, Sani R. Nassif:
Analyzing the impact of process variations on parametric measurements: Novel models and applications. DATE 2009: 375-380 - [c84]Rouwaida Kanj, Rajiv V. Joshi, Chad Adams, James D. Warnock, Sani R. Nassif:
An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects. ICCAD 2009: 497-504 - [c83]Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif:
Simultaneous layout migration and decomposition for double patterning technology. ICCAD 2009: 595-600 - [c82]Aditya Bansal, Rama N. Singh, Rouwaida Kanj, Saibal Mukhopadhyay, Jin-Fuw Lee, Emrah Acar, Amith Singhee, Keunwoo Kim, Ching-Te Chuang, Sani R. Nassif, Fook-Luen Heng, Koushik K. Das:
Yield estimation of SRAM circuits using "Virtual SRAM Fab". ICCAD 2009: 631-636 - [c81]Rouwaida Kanj, Rajiv V. Joshi, Jente B. Kuang, J. Kim, Mesut Meterelliyoz, William R. Reohr, Sani R. Nassif, Kevin J. Nowka:
Statistical yield analysis of silicon-on-insulator embedded DRAM. ISQED 2009: 190-194 - [c80]Nancy Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi:
The impact of BEOL lithography effects on the SRAM cell performance and yield. ISQED 2009: 607-612 - 2008
- [b1]Michael Orshansky, Sani R. Nassif, Duane S. Boning:
Design for Manufacturability and Statistical Design - A Constructive Approach. Series on integrated circuits and systems, Springer 2008, ISBN 978-0-387-30928-6, pp. I-XIV, 1-310 - [j14]Kanak Agarwal, Sani R. Nassif:
The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies. IEEE Trans. Very Large Scale Integr. Syst. 16(1): 86-97 (2008) - [c79]Sani R. Nassif:
Technology modeling and characterization beyond the 45nm node. ASP-DAC 2008: 219 - [c78]Sani R. Nassif:
Power grid analysis benchmarks. ASP-DAC 2008: 376-381 - [c77]Rajeshwary Tayade, Sani R. Nassif, Jacob A. Abraham:
Analytical model for the impact of multiple input switching noise on timing. ASP-DAC 2008: 514-517 - [c76]Sani R. Nassif:
Process variability at the 65nm node and beyond. CICC 2008: 1-8 - [c75]Kevin J. Nowka, Sani R. Nassif, Kanak Agarwal:
Characterization and design for variability and reliability. CICC 2008: 341-346 - [c74]Yun Ye, Frank Liu, Sani R. Nassif, Yu Cao:
Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness. DAC 2008: 900-905 - [c73]Diana Marculescu, Sani R. Nassif:
Design Variability: Challenges and Solutions at Microarchitecture-Architecture Level. DATE 2008 - [c72]Xiaoji Ye, Wei Dong, Peng Li, Sani R. Nassif:
MAPS: multi-algorithm parallel circuit simulation. ICCAD 2008: 73-78 - [c71]Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jente B. Kuang, Hung C. Ngo, Nancy Ying Zhou, Weiping Shi, Sani R. Nassif:
SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes. ISLPED 2008: 87-92 - [c70]Rouwaida Kanj, Rajiv V. Joshi, Keunwoo Kim, Richard Williams, Sani R. Nassif:
Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield. ISQED 2008: 702-707 - [c69]Victoria Wang, Kanak Agarwal, Sani R. Nassif, Kevin J. Nowka, Dejan Markovic:
A Design Model for Random Process Variability. ISQED 2008: 734-737 - [c68]Rouwaida Kanj, Zhuo Li, Rajiv V. Joshi, Frank Liu, Sani R. Nassif:
A Root-Finding Method for Assessing SRAM Stability. ISQED 2008: 804-809 - [c67]Sani R. Nassif:
Model to Hardware Matching for nm Scale Technologies. PATMOS 2008: 459 - [c66]Fadi J. Kurdahi, Nikil D. Dutt, Ahmed M. Eltawil, Sani R. Nassif:
Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips. VLSI Design 2008: 14-15 - [e1]Sani R. Nassif, Jaijeet S. Roychowdhury:
2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008. IEEE Computer Society 2008, ISBN 978-1-4244-2820-5 [contents] - [r1]Haihua Su, Sani R. Nassif:
Power Grid Design. Handbook of Algorithms for Physical Design Automation 2008 - 2007
- [c65]Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan:
Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis. DAC 2007: 148-153 - [c64]Kanak Agarwal, Sani R. Nassif:
Characterizing Process Variation in Nanometer CMOS. DAC 2007: 396-399 - [c63]Ritu Singhal, Asha Balijepalli, Anupama R. Subramaniam, Frank Liu, Sani R. Nassif, Yu Cao:
Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation. DAC 2007: 823-828 - [c62]Sani R. Nassif:
Model to Hardware matching for nano-meter scale technologies. ESSCIRC 2007: 28-31 - [c61]Wei Zhao, Yu Cao, Frank Liu, Kanak Agarwal, Dhruva Acharyya, Sani R. Nassif, Kevin J. Nowka:
Rigorous extraction of process variations for 65nm CMOS design. ESSCIRC 2007: 89-92 - [c60]Rajeshwary Tayade, Vijay Kiran Kalyanam, Sani R. Nassif, Michael Orshansky, Jacob A. Abraham:
Estimating path delay distribution considering coupling noise. ACM Great Lakes Symposium on VLSI 2007: 61-66 - [c59]Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif:
Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs. ISQED 2007: 33-40 - [i1]Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif:
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction. CoRR abs/0710.4654 (2007) - 2006
- [j13]T. M. Mak, Sani R. Nassif:
Guest Editors' Introduction: Process Variation and Stochastic Design and Test. IEEE Des. Test Comput. 23(6): 436-437 (2006) - [j12]Kerry Bernstein, David J. Frank, Anne E. Gattiker, Wilfried Haensch, Brian L. Ji, Sani R. Nassif, Edward J. Nowak, Dale J. Pearson, Norman J. Rohrer:
High-performance CMOS variability in the 65-nm regime and beyond. IBM J. Res. Dev. 50(4-5): 433-450 (2006) - [c58]Bhavna Agrawal, Frank Liu, Sani R. Nassif:
Circuit Optimization Using Scale Based Sensitivities. CICC 2006: 635-638 - [c57]Kanak Agarwal, Sani R. Nassif:
Statistical analysis of SRAM cell stability. DAC 2006: 57-62 - [c56]Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif:
Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events. DAC 2006: 69-72 - [c55]Sani R. Nassif, Vijay Pitchumani, Norma Rodriguez, Dennis Sylvester, Clive Bittlestone, Riko Radojcic:
Variation-aware analysis: savior of the nanometer era? DAC 2006: 411-412 - [c54]Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan:
An accurate sparse matrix based framework for statistical static timing analysis. ICCAD 2006: 231-236 - [c53]Bin Zhang, Ari Arapostathis, Sani R. Nassif, Michael Orshansky:
Analytical modeling of SRAM dynamic stability. ICCAD 2006: 315-322 - [c52]Emrah Acar, Kanak Agarwal, Sani R. Nassif:
Characterization of total chip leakage using inverse (reciprocal) gamma distribution. ISCAS 2006 - [c51]Sani R. Nassif, Kanak Agarwal, Emrah Acar:
Methods for estimating decoupling capacitance of nonswitching circuit blocks. ISCAS 2006 - [c50]Sani R. Nassif:
Model to hardware matching: for nano-meter scale technologies. ISLPED 2006: 203-206 - [c49]Fadi J. Kurdahi, Ahmed M. Eltawil, Young-Hwan Park, Rouwaida Kanj, Sani R. Nassif:
System-Level SRAM Yield Enhancement. ISQED 2006: 179-184 - [c48]Praveen Elakkumanan, Jente B. Kuang, Kevin J. Nowka, Ramalingam Sridhar, Rouwaida Kanj, Sani R. Nassif:
SRAM Local Bit Line Access Failure Analyses. ISQED 2006: 204-209 - [c47]Anand Ramalingam, David Z. Pan, Frank Liu, Sani R. Nassif:
Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity. ISQED 2006: 644-649 - 2005
- [j11]Emrah Acar, Anirudh Devgan, Sani R. Nassif:
Leakage and Leakage Sensitivity Computation for Combinational Circuits. J. Low Power Electron. 1(2): 172-181 (2005) - [j10]Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar:
Early-stage power grid analysis for uncertain working modes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(5): 676-682 (2005) - [j9]Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar:
Power grid analysis using random walks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(8): 1204-1224 (2005) - [c46]Sani R. Nassif, Paul S. Zuchowski, Claude Moughanni, Mohamed Moosa, Stephen D. Posluszny, Ward Vercruysse:
The Titanic: what went wrong! DAC 2005: 349-350 - [c45]Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif:
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction. DATE 2005: 958-963 - [c44]Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif:
Benefits and Costs of Power-Gating Technique. ICCD 2005: 559-566 - [c43]Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif:
Power-aware global signaling strategies. ISCAS (1) 2005: 604-607 - [c42]Rajeev R. Rao, David T. Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif:
An efficient surface-based low-power buffer insertion algorithm. ISPD 2005: 86-93 - [c41]Sani R. Nassif, Zhuo Li:
A More Effective CEFF. ISQED 2005: 648-653 - [c40]Ramyanshu Datta, Sani R. Nassif, Robert K. Montoye, Jacob A. Abraham:
Testing and debugging delay faults in dynamic circuits. ITC 2005: 10 - [c39]Anirudh Devgan, Sani R. Nassif:
Power Variability and Its Impact on Design. VLSI Design 2005: 679-682 - 2004
- [j8]Juan Antonio Carballo, Sani R. Nassif:
Impact of Design-Manufacturing Interface on SoC Design Methodologies. IEEE Des. Test Comput. 21(3): 183-191 (2004) - [j7]Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif:
A methodology for the simultaneous design of supply and signal networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12): 1614-1624 (2004) - [c38]Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula:
Variational delay metrics for interconnect timing analysis. DAC 2004: 381-384 - [c37]Sani R. Nassif, Duane S. Boning, Nagib Hakim:
The care and feeding of your statistical static timer. ICCAD 2004: 138-139 - [c36]Haifeng Qian, Joseph N. Kozhaya, Sani R. Nassif, Sachin S. Sapatnekar:
A chip-level electrostatic discharge simulation strategy. ICCAD 2004: 315-318 - [c35]Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif:
Approaches to run-time and standby mode leakage reduction in global buses. ISLPED 2004: 188-193 - [c34]Sani R. Nassif:
The impact of variability on power. ISLPED 2004: 350 - [c33]Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar:
Early-stage power grid analysis for uncertain working modes. ISPD 2004: 132-137 - 2003
- [j6]Sani R. Nassif, Soha Hassoun:
Guest Editors' Introduction: On-Chip Power Distribution Networks. IEEE Des. Test Comput. 20(3): 5-6 (2003) - [j5]Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif:
Optimal decoupling capacitor sizing and placement for standard-cell layout designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4): 428-436 (2003) - [c32]Emrah Acar, Ravishankar Arunachalam, Sani R. Nassif:
Predicting short circuit power from timing models. ASP-DAC 2003: 277-282 - [c31]Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar:
Random walks in a supply network. DAC 2003: 93-98 - [c30]Haihua Su, Emrah Acar, Sani R. Nassif:
Power grid reduction based on algebraic multigrid principles. DAC 2003: 109-112 - [c29]Haihua Su, Frank Liu, Anirudh Devgan, Emrah Acar, Sani R. Nassif:
Full chip leakage estimation considering power supply and temperature variations. ISLPED 2003: 78-83 - [c28]Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns:
Leakage and leakage sensitivity computation for combinational circuits. ISLPED 2003: 96-99 - [c27]Ravishankar Arunachalam, Emrah Acar, Sani R. Nassif:
Optimal shielding/spacing metrics for low power design. ISVLSI 2003: 167-172 - 2002
- [j4]Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm:
A multigrid-like technique for power grid analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10): 1148-1160 (2002) - [c26]Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif:
Congestion-driven codesign of power and signal networks. DAC 2002: 64-69 - [c25]Emrah Acar, Sani R. Nassif, Lawrence T. Pileggi:
A Linear-Centric Simulation Framework for Parametric Fluctuations. DATE 2002: 568-575 - [c24]Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long:
Static timing analysis based circuit-limited-yield estimation. ISCAS (5) 2002: 81-84 - [c23]Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif:
An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts. ISPD 2002: 68-73 - [c22]Emrah Acar, Sani R. Nassif, Ying Liu, Lawrence T. Pileggi:
Time-Domain Simulation of Variational Interconnect Models. ISQED 2002: 419-424 - [c21]Juan Antonio Carballo, Sani R. Nassif:
Impact of Technology in Power-Grid-Induced Noise. PATMOS 2002: 45-54 - [c20]Sani R. Nassif, Onsi Fakhouri:
Technology trends in power-grid-induced noise. SLIP 2002: 55-59 - [c19]Duane S. Boning, Joseph Panganiban, Karen Gonzalez-Valentin, Sani R. Nassif, Chandler McDowell, Anne E. Gattiker, Frank Liu:
Test structures for delay variability. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 109 - 2001
- [c18]Sani R. Nassif:
Modeling and forecasting of manufacturing variations (embedded tutorial). ASP-DAC 2001: 145-150 - [c17]Hidetoshi Onodera, Andrew B. Kahng, Wayne Wei-Ming Dai, Sani R. Nassif, Juho Kim, Akira Tanabe, Toshihiro Hattori:
Beyond the red brick wall (panel): challenges and solutions in 50nm physical design. ASP-DAC 2001: 267-268 - [c16]Sani R. Nassif:
Modeling and analysis of manufacturing variations. CICC 2001: 223-228 - [c15]Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm:
Multigrid-Like Technique for Power Grid Analysis. ICCAD 2001: 480-487 - [c14]Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm:
I/O buffer placement methodology for ASICs. ICECS 2001: 245-248 - [c13]Emrah Acar, Lawrence T. Pileggi, Sani R. Nassif, Ying Liu:
Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations. ISQED 2001: 431-436 - [c12]Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long:
Timing Yield Estimation from Static Timing Analysis. ISQED 2001: 437-442 - 2000
- [c11]Sani R. Nassif, Joseph N. Kozhaya:
Fast power grid simulation. DAC 2000: 156-161 - [c10]Ying Liu, Sani R. Nassif, Lawrence T. Pileggi, Andrzej J. Strojwas:
Impact of interconnect variations on the clock skew of a gigahertz microprocessor. DAC 2000: 168-171 - [c9]Vikas Mehrotra, Shiou Lin Sam, Duane S. Boning, Anantha P. Chandrakasan, Rakesh Vallishayee, Sani R. Nassif:
A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance. DAC 2000: 172-175 - [c8]N. S. Nagaraj, Andrzej J. Strojwas, Sani R. Nassif, Ray Hokinson, Tak Young, Wonjae L. Kang, David Overhauser, Sung-Mo Kang:
When bad things happen to good chips (panel session). DAC 2000: 736-737 - [c7]Sani R. Nassif:
Designing Closer to the Edge. DATE 2000: 636-637 - [c6]Sani R. Nassif, Joseph N. Kozhaya:
Multi-grid methods for power grid simulation. ISCAS 2000: 457-460 - [c5]Sani R. Nassif:
Design for Variability in DSM Technologies. ISQED 2000: 451-454
1990 – 1999
- 1999
- [c4]Sani R. Nassif, Tuyen V. Nguyen:
SOI technology and tools (abstract). ICCAD 1999: 459 - 1998
- [c3]A. Carvalho, Fadi J. Kurdahi, Sani R. Nassif:
IR and Thermal Estimation Tools, with Applications to the GUTS 1GHz Processor. SBCCI 1998: 236-239 - 1997
- [c2]David P. LaPotin, Uttam Ghoshal, Eli Chiprout, Sani R. Nassif:
Physical design challenges for performance. ISPD 1997: 225-226
1980 – 1989
- 1986
- [j3]Sani R. Nassif, Andrzej J. Strojwas, Stephen W. Director:
A Methodology for Worst-Case Analysis of Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(1): 104-113 (1986) - [c1]Luís M. Vidigal, Sani R. Nassif, Stephen W. Director:
CINNAMON: coupled integration and nodal analysis of MOS networks. DAC 1986: 179-185 - 1984
- [j2]David P. LaPotin, Sani R. Nassif, Jayanth V. Rajan, Michael L. Bushnell, John A. Nestor:
DIF: A framework for VLSI multi-level representation. Integr. 2(3): 227-241 (1984) - [j1]Sani R. Nassif, Andrzej J. Strojwas, Stephen W. Director:
FABRICS II: A Statistically Based IC Fabrication Process Simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3(1): 40-46 (1984)
Coauthor Index
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