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ORCIDRobert Reutemann
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2010 – 2019
- 2014
[j6]Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, Troy J. Beukema, William R. Kelly, Hui H. Xu, David Freitas, Andrea Prati, Daniele Gardellini, Robert Reutemann, Giovanni Cervelli, Juergen Hertle, Matthew Baecher, Jon Garlett, Pier Andrea Francese
, John F. Ewen, David Hanson, Daniel W. Storaska, Mounir Meghelli:
A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology. IEEE J. Solid State Circuits 49(11): 2474-2489 (2014)- 2012
- [j5]Thomas Toifl, Christian Menolfi, Michael Ruegg, Robert Reutemann, Daniel Dreps, Troy J. Beukema, Andrea Prati, Daniele Gardellini, Marcel A. Kossel, Peter Buchmann, Matthias Braendli, Pier Andrea Francese, Thomas Morf:
A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS. IEEE J. Solid State Circuits 47(4): 897-910 (2012) - 2010
- [j4]Robert Reutemann, Michael Ruegg, Fran Keyser, John Bergkvist, Daniel Dreps, Thomas Toifl, Martin L. Schmatz:
A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS. IEEE J. Solid State Circuits 45(12): 2850-2860 (2010) - [c2]Robert Reutemann, Michael Ruegg, Fran Keyser, John Bergkvist, Daniel Dreps, Thomas Toifl, Martin L. Schmatz:
A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS. ISSCC 2010: 160-161
2000 – 2009
- 2007
- [c1]Chiara Martelli, Robert Reutemann, Christian Benkeser, Qiuting Huang:
A 50mW HSDPA Baseband Receiver ASIC with Multimode Digital Front-End. ISSCC 2007: 260-601 - 2006
- [j3]Thomas Toifl, Christian Menolfi, Michael Ruegg, Robert Reutemann, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Martin L. Schmatz:
A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology. IEEE J. Solid State Circuits 41(4): 954-965 (2006) - 2005
- [j2]Thomas Toifl, Christian Menolfi, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Robert Reutemann, Michael Ruegg, Martin L. Schmatz, Jonas R. M. Weiss:
A 0.94-ps-RMS-jitter 0.016-mm2 2.5-GHz multiphase generator PLL with 360° digitally programmable phase shift for 10-Gb/s serial links. IEEE J. Solid State Circuits 40(12): 2700-2712 (2005) - 2002
- [j1]Michael Oberle, Robert Reutemann, Jürgen Hertle, Qiuting Huang:
A 10-mW two-channel fully integrated system-on-chip for eddy-current position sensing [in biomedical devices]. IEEE J. Solid State Circuits 37(7): 916-925 (2002)
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