"A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with ..."

Robert Reutemann et al. (2010)

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DOI: 10.1109/ISSCC.2010.5434008

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Robert Reutemann, Michael Ruegg, Fran Keyser, John Bergkvist, Daniel Dreps, Thomas Toifl, Martin L. Schmatz:
A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS. ISSCC 2010: 160-161

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