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Jaehoon Lee 0005
Person information
- affiliation: Samsung Electronics, Hwaseong, Korea
Other persons with the same name
- Jaehoon Lee — disambiguation page
- Jaehoon Lee 0001 — Google Brain
- Jaehoon Lee 0002 — Yonsei University, Korea
- Jaehoon Lee 0003 — University of Utah, Salt Lake City, UT, USA
- Jaehoon Lee 0004 — Kyushu Institute of Technology, Fukuoka, Japan
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2020 – today
- 2024
- [j2]Jaehong Jung, Seunghyun Oh, Joomyoung Kim, Jinhyeon Lee, Wonkang Kim, Euiyoung Park, Seungyong Bae, Seungjin Kim, Jaehoon Lee, Yelim Youn, Yeongcheol Jeong, Sungsik Park, Kyungsoo Lee, Yong Lim, Junho Huh, Jongwoo Lee:
A Fully Integrated, Low-Noise, Cost-Effective Single-Crystal-Oscillator-Based Clock Management IC in 28-nm CMOS. IEEE J. Solid State Circuits 59(6): 1809-1822 (2024) - 2022
- [j1]Barosaim Sung, Hyun-Gi Seok, Jaekwon Kim, Jaehoon Lee, Taejin Jang, Ilhoon Jang, Youngmin Kim, Anna Yu, Jong-Hyun Jang, Jiyoung Lee, Jeongyeol Bae, Euiyoung Park, Sung-Jun Lee, Seokwon Lee, Joohan Kim, Beomkon Kim, Yong Lim, Seunghyun Oh, Jongwoo Lee:
A Single Path Digital-IF Receiver Supporting Inter/Intra 5-CA With a Single Integer LO-PLL in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 57(12): 3646-3655 (2022) - [c10]Jaehong Jung, Seunghyun Oh, Joo-Myoung Kim, Gihyeok Ha, Jinhyeon Lee, Seungjin Kim, Euiyoung Park, Jaehoon Lee, Yelim Yoon, Seungyong Bae, Wonkang Kim, Yong Lim, Kyungsoo Lee, Junho Huh, Jongwoo Lee, Thomas Byunghak Cho:
A Single-Crystal-Oscillator-Based Clock-Management IC with 18× Start-Up Time Reduction and 0.68ppm/ºC Duty-Cycled Machine-Learning-Based RCO Calibration. ISSCC 2022: 58-60 - [c9]Barosaim Sung, Hyun-Gi Seok, Jaekwon Kim, Jaehoon Lee, Taejin Jang, Ilhoon Jang, Youngmin Kim, Anna Yu, Jong-Hyun Jang, Jiyoung Lee, Jeongyeol Bae, Euiyoung Park, Sung-Jun Lee, Seokwon Lee, Joohan Kim, Beomkon Kim, Yong Lim, Seunghyun Oh, Jongwoo Lee, Thomas Byunghak Cho, Inyup Kang:
A Single-Path Digital-IF Receiver Supporting Inter/Intra 5-CA with a Single Integer LO-PLL in 14nm CMOS FinFET. ISSCC 2022: 440-442 - [c8]Jaehoon Lee, Yong Lim, Jongmi Lee, Taejin Jang, Kwonwoo Kang, Jongpil Cho, Seunghyun Oh, Jongwoo Lee:
A 0.56mW 63.6dB SNDR 250MS/s SAR ADC in 8nm FinFET. VLSI Technology and Circuits 2022: 90-92 - 2021
- [c7]Suk Han Lee, Shinhaeng Kang, Jaehoon Lee, Hyeonsu Kim, Eojin Lee, Seungwoo Seo, Hosang Yoon, Seungwon Lee, Kyounghwan Lim, Hyunsung Shin, Jinhyun Kim, Seongil O, Anand Iyer, David Wang, Kyomin Sohn, Nam Sung Kim:
Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product. ISCA 2021: 43-56 - [c6]Jongsoo Lee, Byoungjoong Kang, Seongwon Joo, Seokwon Lee, Joongho Lee, Seunghoon Kang, Ikkyun Jo, Suseop Ahn, Jaeseung Lee, Jeongyeol Bae, Won Ko, Woniun Jung, Sangho Lee, Sangsung Lee, Euiyoung Park, Sungiun Lee, Jeongkyun Woo, Jaehoon Lee, Yanghoon Lee, Kyungmin Lee, Jongwoo Lee, Thomas Byunghak Cho, Inyup Kang:
6.1 A Low-Power and Low-Cost 14nm FinFET RFIC Supporting Legacy Cellular and 5G FR1. ISSCC 2021: 90-92 - [c5]Chilun Lo, Jongmi Lee, Yong Lim, Younghyun Yoon, Hyunseok Hwang, Jaehoon Lee, Moo-Yeol Choi, Myungjin Lee, Seunghyun Oh, Jongwoo Lee:
10.1 A 116μ W 104.4dB-DR 100.6dB-SNDR CT Δ∑ Audio ADC Using Tri-Level Current-Steering DAC with Gate-Leakage Compensated Off-Transistor-Based Bias Noise Filter. ISSCC 2021: 164-166 - [c4]Young-Cheon Kwon, Suk Han Lee, Jaehoon Lee, Sang-Hyuk Kwon, Je-Min Ryu, Jong-Pil Son, Seongil O, Hak-soo Yu, Haesuk Lee, Soo Young Kim, Youngmin Cho, Jin Guk Kim, Jongyoon Choi, Hyunsung Shin, Jin Kim, BengSeng Phuah, Hyoungmin Kim, Myeong Jun Song, Ahn Choi, Daeho Kim, Sooyoung Kim, Eun-Bong Kim, David Wang, Shinhaeng Kang, Yuhwan Ro, Seungwoo Seo, Joon-Ho Song, Jaeyoun Youn, Kyomin Sohn, Nam Sung Kim:
25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications. ISSCC 2021: 350-352 - 2020
- [c3]Jaehoon Lee, Yong Lim, Barosaim Sung, Seunghyun Oh, Jung-Hoon Chun, Jongwoo Lee:
An Effective Transconductance Controlled Offset Calibration for Dynamic Comparators. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c2]Barosaim Sung, Chilun Lo, Jaehoon Lee, Sangdon Jung, Seungjin Kim, Jaehong Jung, Seungyong Bae, Youngsea Cho, Yong Lim, Dooseok Choi, Myeongcheol Shin, Soonwoo Choi, Byungki Han, Seunghyun Oh, Jongwoo Lee:
A Blocker-Tolerant Direct Sampling Receiver for Wireless Multi-Channel Communication in 14nm FinFET CMOS. A-SSCC 2019: 165-168 - 2017
- [c1]Jongmi Lee, Jongwoo Lee, Chilun Lo, Jaehoon Lee, In-Young Lee, Byungki Han, Seunghyun Oh, Thomas Byunghak Cho:
A reconfigurable analog baseband transformer for multistandard applications in 14nm FinFET CMOS. A-SSCC 2017: 5-8
Coauthor Index
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last updated on 2024-10-17 20:30 CEST by the dblp team
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