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Jaeyoun Youn
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2020 – today
- 2024
- [j2]Jinook Jung, Jun-Han Choi, Kyoung-Jun Roh, Jaewoo Park, Won-Mook Lim, Tae-Sung Kim, Han-Ki Jeong, Myoungbo Kwak, Jaeyoun Youn, Jeong-Don Ihm, Changsik Yoo, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko:
A 4 ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3. IEEE J. Solid State Circuits 59(10): 3307-3316 (2024) - 2023
- [j1]Yesin Ryu, Sung-Gi Ahn, Jae Hoon Lee, Jaewon Park, Yong-Ki Kim, Hyochang Kim, Yeong Geol Song, Han-Won Cho, Sunghye Cho, Seung Ho Song, Haesuk Lee, Useung Shin, Jonghyun Ahn, Je-Min Ryu, Suk Han Lee, Kyounghwan Lim, Jungyu Lee, Jeong Hoan Park, Jae-Seung Jeong, Sunghwan Jo, Dajung Cho, Sooyoung Kim, Minsu Lee, Hyunho Kim, Minhwan Kim, Jae San Kim, Jinah Kim, Hyun Gil Kang, Myung-Kyu Lee, Sung-Rae Kim, Young-Cheon Kwon, Young-Yong Byun, Kijun Lee, Sangkil Park, Jaeyoun Youn, Myeong-O. Kim, Kyomin Sohn, SangJoon Hwang, JooYoung Lee:
A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features. IEEE J. Solid State Circuits 58(4): 1051-1061 (2023) - [c4]Jinook Jung, Jun-Han Choi, Kyoung-Jun Roh, Jaewoo Park, Won-Mook Lim, Tae-Sung Kim, Han-Ki Jeong, Myoungbo Kwak, Jaeyoun Youn, Jeong-Don Ihm, Changsik Yoo, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko:
A 4ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3. A-SSCC 2023: 1-3 - 2022
- [c3]Yesin Ryu, Young-Cheon Kwon, Jae Hoon Lee, Sung-Gi Ahn, Jaewon Park, Kijun Lee, Yu Ho Choi, Han-Won Cho, Jae San Kim, Jungyu Lee, Haesuk Lee, Seung Ho Song, Je-Min Ryu, Yeong Ho Yun, Useung Shin, Dajung Cho, Jeong Hoan Park, Jae-Seung Jeong, Suk Han Lee, Kyounghwan Lim, Tae-Sung Kim, Kyungmin Kim, Yu Jin Cha, Ik Joo Lee, Tae Kyu Byun, Han Sik Yoo, Yeong Geol Song, Myung-Kyu Lee, Sunghye Cho, Sung-Rae Kim, Ji-Min Choi, Hyoungmin Kim, Soo Young Kim, Jaeyoun Youn, Myeong-O. Kim, Kyomin Sohn, SangJoon Hwang, JooYoung Lee:
A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features. VLSI Technology and Circuits 2022: 130-131 - 2021
- [c2]Young-Cheon Kwon, Suk Han Lee, Jaehoon Lee, Sang-Hyuk Kwon, Je-Min Ryu, Jong-Pil Son, Seongil O, Hak-soo Yu, Haesuk Lee, Soo Young Kim, Youngmin Cho, Jin Guk Kim, Jongyoon Choi, Hyunsung Shin, Jin Kim, BengSeng Phuah, Hyoungmin Kim, Myeong Jun Song, Ahn Choi, Daeho Kim, Sooyoung Kim, Eun-Bong Kim, David Wang, Shinhaeng Kang, Yuhwan Ro, Seungwoo Seo, Joon-Ho Song, Jaeyoun Youn, Kyomin Sohn, Nam Sung Kim:
25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications. ISSCC 2021: 350-352
2010 – 2019
- 2012
- [c1]Yong-Cheol Bae, Joon-Young Park, Sang Jae Rhee, Seung-Bum Ko, Yonggwon Jeong, Kwang-Sook Noh, Young Hoon Son, Jaeyoun Youn, Yonggyu Chu, Hyunyoon Cho, Mijo Kim, Daesik Yim, Hyo-Chang Kim, Sang-Hoon Jung, Hye-In Choi, Sungmin Yim, Jung-Bae Lee, Joo-Sun Choi, Kyungseok Oh:
A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme. ISSCC 2012: 44-46
Coauthor Index
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last updated on 2024-10-08 20:34 CEST by the dblp team
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