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ORCIDNorman P. Jouppi
Norm Jouppi
Person information
- affiliation: Google, Mountain View, CA, USA
- award (2015): Eckert-Mauchly Award
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2020 – today
- 2024
[c93]Hong Liu, Ryohei Urata, Kevin Yasumura, Xiang Zhou, Roy Bannon, Jill Berger, Pedram Dashti, Norm Jouppi, Cedric F. Lam, Sheng Li, Erji Mao, Daniel Nelson, George Papen, Muhammad Mukarram Bin Tariq, Amin Vahdat:
Reconfigurable Lightwave Fabrics for ML Supercomputers. OFC 2024: 1-3- 2023
- [c92]Sheng Li, Garrett Andersen, Tao Chen, Liqun Cheng, Julian Grady, Da Huang, Quoc V. Le, Andrew Li, Xin Li, Yang Li, Chen Liang, Yifeng Lu, Yun Ni
, Ruoming Pang, Mingxing Tan, Martin Wicke, Gang Wu, Shengqi Zhu, Parthasarathy Ranganathan, Norman P. Jouppi:
Hyperscale Hardware Optimized Neural Architecture Search. ASPLOS (3) 2023: 343-358 - [c91]Norman P. Jouppi, Andy Swing:
A Machine Learning Supercomputer with an Optically Reconfigurable Interconnect and Embeddings Support. HCS 2023: 1-24 - [c90]Norman P. Jouppi, George Kurian, Sheng Li, Peter C. Ma, Rahul Nagarajan, Lifeng Nai, Nishant Patil, Suvinay Subramanian, Andy Swing, Brian Towles, Cliff Young, Xiang Zhou, Zongwei Zhou, David A. Patterson:
TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings. ISCA 2023: 82:1-82:14 - [c89]Hong Liu, Ryohei Urata, Kevin Yasumura, Xiang Zhou, Roy Bannon, Jill Berger, Pedram Dashti, Norm Jouppi, Cedric F. Lam, Sheng Li, Erji Mao, Daniel Nelson, George Papen, Muhammad Mukarram Bin Tariq, Amin Vahdat:
Lightwave Fabrics: At-Scale Optical Circuit Switching for Datacenter and Machine Learning Systems. SIGCOMM 2023: 499-515 - [i7]Norman P. Jouppi, George Kurian, Sheng Li, Peter C. Ma, Rahul Nagarajan, Lifeng Nai, Nishant Patil, Suvinay Subramanian, Andy Swing, Brian Towles, Cliff Young, Xiang Zhou, Zongwei Zhou, David A. Patterson:
TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings. CoRR abs/2304.01433 (2023) - [i6]Dana Vantrease, Robert Schreiber, Matteo Monchiero, Moray McLaren, Norman P. Jouppi, Marco Fiorentino, Al Davis, Nathan L. Binkert, Raymond G. Beausoleil, Jung Ho Ahn:
RETROSPECTIVE: Corona: System Implications of Emerging Nanophotonic Technology. CoRR abs/2306.15688 (2023) - [i5]Dana Vantrease, Robert Schreiber, Matteo Monchiero, Moray McLaren, Norman P. Jouppi, Marco Fiorentino, Al Davis, Nathan L. Binkert, Raymond G. Beausoleil, Jung Ho Ahn:
Corona: System Implications of Emerging Nanophotonic Technology. CoRR abs/2307.06294 (2023) - [i4]Jordan Dotzel, Gang Wu, Andrew Li, Muhammad Umar, Yun Ni, Mohamed S. Abdelfattah, Zhiru Zhang, Liqun Cheng, Martin G. Dixon, Norman P. Jouppi, Quoc V. Le, Sheng Li:
FLIQS: One-Shot Mixed-Precision Floating-Point and Integer Quantization Search. CoRR abs/2308.03290 (2023) - 2021
- [j41]Thomas Norrie, Nishant Patil, Doe Hyun Yoon, George Kurian, Sheng Li, James Laudon, Cliff Young, Norman P. Jouppi, David A. Patterson:
The Design Process for Google's Training Chips: TPUv2 and TPUv3. IEEE Micro 41(2): 56-63 (2021) - [c88]Sheng Li, Mingxing Tan, Ruoming Pang, Andrew Li, Liqun Cheng, Quoc V. Le, Norman P. Jouppi:
Searching for Fast Model Families on Datacenter Accelerators. CVPR 2021: 8085-8095 - [c87]Tianqi Tang, Sheng Li, Lifeng Nai, Norman P. Jouppi, Yuan Xie:
NeuroMeter: An Integrated Power, Area, and Timing Modeling Framework for Machine Learning Accelerators Industry Track Paper. HPCA 2021: 841-853 - [c86]Norman P. Jouppi, Doe Hyun Yoon, Matthew Ashcraft, Mark Gottscho, Thomas B. Jablin, George Kurian, James Laudon, Sheng Li, Peter C. Ma, Xiaoyu Ma, Thomas Norrie, Nishant Patil, Sushma Prasad, Cliff Young, Zongwei Zhou, David A. Patterson:
Ten Lessons From Three Generations Shaped Google's TPUv4i : Industrial Product. ISCA 2021: 1-14 - [i3]Sheng Li, Mingxing Tan, Ruoming Pang, Andrew Li, Liqun Cheng, Quoc V. Le, Norman P. Jouppi:
Searching for Fast Model Families on Datacenter Accelerators. CoRR abs/2102.05610 (2021) - 2020
- [j40]Norman P. Jouppi, Doe Hyun Yoon, George Kurian, Sheng Li, Nishant Patil, James Laudon, Cliff Young, David A. Patterson:
A domain-specific supercomputer for training deep neural networks. Commun. ACM 63(7): 67-78 (2020) - [c85]Thomas Norrie, Nishant Patil, Doe Hyun Yoon, George Kurian, Sheng Li, James Laudon, Cliff Young, Norman P. Jouppi, David A. Patterson:
Google's Training Chips Revealed: TPUv2 and TPUv3. Hot Chips Symposium 2020: 1-70 - [i2]Sameer Kumar, Norm Jouppi:
Highly Available Data Parallel ML training on Mesh Networks. CoRR abs/2011.03605 (2020)
2010 – 2019
- 2018
- [j39]Norman P. Jouppi, Cliff Young, Nishant Patil, David A. Patterson:
A domain-specific architecture for deep neural networks. Commun. ACM 61(9): 50-59 (2018) - [j38]Norman P. Jouppi, Cliff Young, Nishant Patil, David A. Patterson:
Motivation for and Evaluation of the First Tensor Processing Unit. IEEE Micro 38(3): 10-19 (2018) - 2017
- [c84]Norman P. Jouppi, Cliff Young, Nishant Patil, David A. Patterson, Gaurav Agrawal, Raminder Bajwa, Sarah Bates, Suresh Bhatia, Nan Boden, Al Borchers, Rick Boyle, Pierre-luc Cantin, Clifford Chao, Chris Clark, Jeremy Coriell, Mike Daley, Matt Dau, Jeffrey Dean, Ben Gelb, Tara Vazir Ghaemmaghami, Rajendra Gottipati, William Gulland, Robert Hagmann, C. Richard Ho, Doug Hogberg, John Hu, Robert Hundt, Dan Hurt, Julian Ibarz, Aaron Jaffey, Alek Jaworski, Alexander Kaplan, Harshit Khaitan, Daniel Killebrew, Andy Koch, Naveen Kumar, Steve Lacy, James Laudon, James Law, Diemthu Le, Chris Leary, Zhuyuan Liu, Kyle Lucke, Alan Lundin, Gordon MacKean, Adriana Maggiore, Maire Mahony, Kieran Miller, Rahul Nagarajan, Ravi Narayanaswami, Ray Ni, Kathy Nix, Thomas Norrie, Mark Omernick, Narayana Penukonda, Andy Phelps, Jonathan Ross, Matt Ross, Amir Salek, Emad Samadiani, Chris Severn, Gregory Sizikov, Matthew Snelham, Jed Souter, Dan Steinberg, Andy Swing, Mercedes Tan, Gregory Thorson, Bo Tian, Horia Toma, Erick Tuttle, Vijay Vasudevan, Richard Walter, Walter Wang, Eric Wilcox, Doe Hyun Yoon:
In-Datacenter Performance Analysis of a Tensor Processing Unit. ISCA 2017: 1-12 - [i1]Norman P. Jouppi, Cliff Young, Nishant Patil, David A. Patterson, Gaurav Agrawal, Raminder Bajwa, Sarah Bates, Suresh Bhatia, Nan Boden, Al Borchers, Rick Boyle, Pierre-luc Cantin, Clifford Chao, Chris Clark, Jeremy Coriell, Mike Daley, Matt Dau, Jeffrey Dean, Ben Gelb, Tara Vazir Ghaemmaghami, Rajendra Gottipati, William Gulland, Robert Hagmann, C. Richard Ho, Doug Hogberg, John Hu, Robert Hundt, Dan Hurt, Julian Ibarz, Aaron Jaffey, Alek Jaworski, Alexander Kaplan, Harshit Khaitan, Andy Koch, Naveen Kumar, Steve Lacy, James Laudon, James Law, Diemthu Le, Chris Leary, Zhuyuan Liu, Kyle Lucke, Alan Lundin, Gordon MacKean, Adriana Maggiore, Maire Mahony, Kieran Miller, Rahul Nagarajan, Ravi Narayanaswami, Ray Ni, Kathy Nix, Thomas Norrie, Mark Omernick, Narayana Penukonda, Andy Phelps, Jonathan Ross, Amir Salek, Emad Samadiani, Chris Severn, Gregory Sizikov, Matthew Snelham, Jed Souter, Dan Steinberg, Andy Swing, Mercedes Tan, Gregory Thorson, Bo Tian, Horia Toma, Erick Tuttle, Vijay Vasudevan, Richard Walter, Walter Wang, Eric Wilcox, Doe Hyun Yoon:
In-Datacenter Performance Analysis of a Tensor Processing Unit. CoRR abs/1704.04760 (2017) - 2016
- [j37]Onur Mutlu, Rich Belgard, Thomas R. Gross, Norman P. Jouppi, John L. Hennessy, Steven A. Przybylski, Chris Rowen, Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Tse-Yu Yeh, Andy Wolfe:
Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor. IEEE Micro 36(4): 70-85 (2016) - 2015
- [j36]Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas:
CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models. IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1254-1267 (2015) - [c83]Ke Chen, Sheng Li, Jung Ho Ahn, Naveen Muralimanohar, Jishen Zhao, Cong Xu, Seongil O, Yuan Xie, Jay B. Brockman, Norman P. Jouppi:
History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures. ICS 2015: 251-261 - 2014
- [j35]Jue Wang, Xiangyu Dong, Yuan Xie, Norman P. Jouppi:
Endurance-aware cache line management for non-volatile caches. ACM Trans. Archit. Code Optim. 11(1): 4:1-4:25 (2014) - [j34]HanBin Yoon, Justin Meza, Naveen Muralimanohar, Norman P. Jouppi, Onur Mutlu:
Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories. ACM Trans. Archit. Code Optim. 11(4): 40:1-40:25 (2014) - 2013
- [j33]Sheng Li, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, Norman P. Jouppi:
The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing. ACM Trans. Archit. Code Optim. 10(1): 5:1-5:29 (2013) - [j32]Xiangyu Dong, Norman P. Jouppi, Yuan Xie:
A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies. ACM Trans. Archit. Code Optim. 10(4): 23:1-23:22 (2013) - [c82]Cong Xu, Dimin Niu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie:
Understanding the trade-offs in multi-level cell ReRAM memory design. DAC 2013: 108:1-108:6 - [c81]Jue Wang, Xiangyu Dong, Yuan Xie, Norman P. Jouppi:
i2WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations. HPCA 2013: 234-245 - [c80]Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie:
Design of cross-point metal-oxide ReRAM emphasizing reliability and cost. ICCAD 2013: 17-23 - [c79]Jung Ho Ahn, Sheng Li, Seongil O, Norman P. Jouppi:
McSimA+: A manycore simulator with application-level+ simulation and detailed microarchitecture modeling. ISPASS 2013: 74-85 - [c78]Xiangyu Dong, Norman P. Jouppi, Yuan Xie:
A circuit-architecture co-optimization framework for evaluating emerging memory hierarchies. ISPASS 2013: 140-141 - [c77]Jishen Zhao, Sheng Li, Doe Hyun Yoon, Yuan Xie, Norman P. Jouppi:
Kiln: closing the performance gap between systems with and without persistence support. MICRO 2013: 421-432 - [c76]Doe Hyun Yoon, Jichuan Chang, Robert S. Schreiber, Norman P. Jouppi:
Practical nonvolatile multilevel-cell phase change memory. SC 2013: 21:1-21:12 - 2012
- [j31]Doe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi, Mattan Erez:
Free-p: A Practical End-to-End Nonvolatile Memory Protection Mechanism. IEEE Micro 32(3): 79-87 (2012) - [j30]Nathan L. Binkert, Al Davis, Norman P. Jouppi, Moray McLaren, Naveen Muralimanohar, Robert Schreiber, Jung Ho Ahn:
Optical High Radix Switch Design. IEEE Micro 32(3): 100-109 (2012) - [j29]Jung Ho Ahn, Norman P. Jouppi, Christos Kozyrakis, Jacob Leverich, Robert S. Schreiber:
Improving System Energy Efficiency with Memory Rank Subsetting. ACM Trans. Archit. Code Optim. 9(1): 4:1-4:28 (2012) - [j28]Xiangyu Dong, Cong Xu, Yuan Xie, Norman P. Jouppi:
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(7): 994-1007 (2012) - [c75]Ke Chen, Sheng Li, Naveen Muralimanohar, Jung Ho Ahn, Jay B. Brockman, Norman P. Jouppi:
CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory. DATE 2012: 33-38 - [c74]Niladrish Chatterjee, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi:
Staged Reads: Mitigating the impact of DRAM writes on DRAM reads. HPCA 2012: 41-52 - [c73]Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas:
CACTI-IO: CACTI with off-chip power-area-timing models. ICCAD 2012: 294-301 - [c72]Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi:
LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems. ISCA 2012: 285-296 - [c71]Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie:
Design trade-offs for high density cross-point resistive memory. ISLPED 2012: 209-214 - [c70]Sheng Li, Doe Hyun Yoon, Ke Chen, Jishen Zhao, Jung Ho Ahn, Jay B. Brockman, Yuan Xie, Norman P. Jouppi:
MAGE: adaptive granularity and ECC for resilient and power efficient memory systems. SC 2012: 33 - 2011
- [b1]Rajeev Balasubramonian, Norman P. Jouppi, Naveen Muralimanohar:
Multi-Core Cache Hierarchies. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2011, ISBN 978-3-031-00606-7 - [j27]Norman P. Jouppi:
DRAM errors in the wild: technical perspective. Commun. ACM 54(2): 99 (2011) - [j26]Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi:
Hybrid checkpointing using emerging nonvolatile memories for future exascale systems. ACM Trans. Archit. Code Optim. 8(2): 6:1-6:29 (2011) - [c69]Cong Xu, Xiangyu Dong, Norman P. Jouppi, Yuan Xie:
Design implications of memristor-based RRAM cross-point structures. DATE 2011: 734-739 - [c68]Doe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi, Mattan Erez:
FREE-p: Protecting non-volatile memory against both hard and soft errors. HPCA 2011: 466-477 - [c67]Sheng Li, Ke Chen, Jung Ho Ahn, Jay B. Brockman, Norman P. Jouppi:
CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques. ICCAD 2011: 694-701 - [c66]Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi:
Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems. ISCA 2011: 425-436 - [c65]Nathan L. Binkert, Al Davis, Norman P. Jouppi, Moray McLaren, Naveen Muralimanohar, Robert Schreiber, Jung Ho Ahn:
The role of optics in future high radix switch design. ISCA 2011: 437-448 - [c64]Sheng Li, Kevin T. Lim, Paolo Faraboschi, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi:
System-level integrated server architectures for scale-out datacenters. MICRO 2011: 260-271 - [c63]Sheng Li, Ke Chen, Ming-yu Hsieh, Naveen Muralimanohar, Chad D. Kersey, Jay B. Brockman, Arun F. Rodrigues, Norman P. Jouppi:
System implications of memory reliability in exascale computing. SC 2011: 46:1-46:12 - [p1]Jung Ho Ahn, Raymond G. Beausoleil, Nathan L. Binkert, Al Davis, Marco Fiorentino, Norman P. Jouppi, Moray McLaren, Matteo Monchiero, Naveen Muralimanohar, Robert Schreiber, Dana Vantrease:
CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study. Low Power Networks-on-Chip 2011: 223-254 - 2010
- [c62]Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi:
Rethinking DRAM design and organization for energy-constrained multi-cores. ISCA 2010: 175-186 - [c61]Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi:
Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support. SC 2010: 1-11
2000 – 2009
- 2009
- [j25]Norman P. Jouppi:
Technical perspective - Software and hardware support for deterministic replay of parallel programs. Commun. ACM 52(6): 92 (2009) - [j24]Jung Ho Ahn, Jacob Leverich, Robert S. Schreiber, Norman P. Jouppi:
Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs. IEEE Comput. Archit. Lett. 8(1): 5-8 (2009) - [j23]Michael R. T. Tan, Paul Rosenberg, Jong Souk Yeo, Moray McLaren, Sagi Mathai, Terry Morris, Huei Pei Kuo, Joseph Straznicky, Norman P. Jouppi, Shih-Yuan Wang:
A High-Speed Optical Multidrop Bus for Computer Interconnections. IEEE Micro 29(4): 62-73 (2009) - [j22]Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen:
Introduction to the special issue on the 2008 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'08). SIGARCH Comput. Archit. News 37(2): 1 (2009) - [c60]Norman P. Jouppi:
Resilience Challenges for Exascale Systems. DFT 2009: 379-379 - [c59]Xiangyu Dong, Norman P. Jouppi, Yuan Xie:
PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAM. ICCAD 2009: 269-275 - [c58]Norman P. Jouppi, Yuan Xie:
Emerging technologies and their impact on system design. ISLPED 2009: 427-428 - [c57]Sheng Li, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, Norman P. Jouppi:
McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures. MICRO 2009: 469-480 - [c56]Jung Ho Ahn, Norman P. Jouppi, Christos Kozyrakis, Jacob Leverich, Robert S. Schreiber:
Future scaling of processor-memory interfaces. SC 2009 - [c55]Xiangyu Dong, Naveen Muralimanohar, Norman P. Jouppi, Richard Kaufmann, Yuan Xie:
Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems. SC 2009 - 2008
- [j21]Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi:
Architecting Efficient Interconnects for Large Caches with CACTI 6.0. IEEE Micro 28(1): 69-79 (2008) - [j20]Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen:
Introduction to the special issue on the 2007 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'07). SIGARCH Comput. Archit. News 36(2): 1 (2008) - [c54]Michael R. T. Tan, Paul Rosenberg, Jong Souk Yeo, Moray McLaren, Sagi Mathai, Terry Morris, Joseph Straznicky, Norman P. Jouppi, Huei Pei Kuo, Shih-Yuan Wang, Scott Lerner, Pavel Kornilovich, Neal Meyer, Robert Bicknell, Charles Otis, Len Seals:
A High-Speed Optical Multi-Drop Bus for Computer Interconnections. Hot Interconnects 2008: 3-10 - [c53]Raymond G. Beausoleil, Jung Ho Ahn, Nathan L. Binkert, Al Davis, David Fattal, Marco Fiorentino, Norman P. Jouppi, Moray McLaren, Charles M. Santori, Robert S. Schreiber, S. M. Spillane, Dana Vantrease, Qianfan Xu:
A Nanophotonic Interconnect for High-Performance Many-Core Computation. Hot Interconnects 2008: 182-189 - [c52]Shyamkumar Thoziyoor, Jung Ho Ahn, Matteo Monchiero, Jay B. Brockman, Norman P. Jouppi:
A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies. ISCA 2008: 51-62 - [c51]Dana Vantrease, Robert Schreiber, Matteo Monchiero, Moray McLaren, Norman P. Jouppi, Marco Fiorentino, Al Davis, Nathan L. Binkert, Raymond G. Beausoleil, Jung Ho Ahn:
Corona: System Implications of Emerging Nanophotonic Technology. ISCA 2008: 153-164 - [c50]Norman P. Jouppi:
System implications of integrated photonics. ISLPED 2008: 183-184 - [c49]Nidhi Aggarwal, James E. Smith, Kewal K. Saluja, Norman P. Jouppi, Parthasarathy Ranganathan:
Implementing high availability memory with a duplication cache. MICRO 2008: 71-82 - 2007
- [j19]Nidhi Aggarwal, Parthasarathy Ranganathan, Norman P. Jouppi, James E. Smith:
Isolation in Commodity Multicore Processors. Computer 40(6): 49-59 (2007) - [j18]Dean M. Tullsen, Rakesh Kumar, Norman P. Jouppi:
Introduction to the special issue on the 2006 workshop on design, analysis, and simulation of chip multiprocessors: (dasCMP'06). SIGARCH Comput. Archit. News 35(1): 2 (2007) - [c48]Shekhar Borkar, Norman P. Jouppi, Per Stenström:
Microprocessors in the era of terascale integration. DATE 2007: 237-242 - [c47]Nidhi Aggarwal, Parthasarathy Ranganathan, Norman P. Jouppi, James E. Smith:
Configurable isolation: building high availability systems with commodity multi-core processors. ISCA 2007: 470-481 - [c46]Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi:
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. MICRO 2007: 3-14 - [c45]Michael S. Schlansker, Nagabhushan Chitlur, Erwin Oertli, Paul M. Stillwell Jr., Linda Rankin, Dennis Bradford, Richard J. Carter, Jayaram Mudigonda, Nathan L. Binkert, Norman P. Jouppi:
High-performance ethernet-based communications for future multi-core processors. SC 2007: 37 - 2006
- [c44]Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi:
Core architecture optimization for heterogeneous chip multiprocessors. PACT 2006: 23-32 - [c43]Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi, Timothy Sherwood, Suleyman Sair:
Improving the performance and power efficiency of shared helpers in CMPs. CASES 2006: 345-356 - [c42]Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker, Brad Calder:
Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers. MICRO 2006: 235-246 - [c41]Christophe Lemuet, Jack Sampson, Jean-Francois Collard, Norman P. Jouppi:
Architecture - The potential energy efficiency of vector acceleration. SC 2006: 77 - 2005
- [j17]Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi, Parthasarathy Ranganathan:
Heterogeneous Chip Multiprocessors. Computer 38(11): 32-38 (2005) - [j16]Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen:
Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'05). SIGARCH Comput. Archit. News 33(4): 4 (2005) - [j15]Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker:
Fast synchronization for chip multiprocessors. SIGARCH Comput. Archit. News 33(4): 64-69 (2005) - [j14]Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi, Suleyman Sair, Timothy Sherwood:
Dynamically configurable shared CMP helper engines for improved performance. SIGARCH Comput. Archit. News 33(4): 70-79 (2005) - [c40]Parthasarathy Ranganathan, Norman P. Jouppi:
Enterprise IT Trends and Implications for Architecture Research. HPCA 2005: 253-256 - [c39]Norman P. Jouppi, Stan Thomas:
Telepresence Systems With Automatic Preservation of User Head Height, Local Rotation, and Remote Translation. ICRA 2005: 62-68 - [c38]Norman P. Jouppi:
The Future Evolution of High-Performance Microprocessors. MICRO 2005: 155 - [c37]Jean-Francois Collard, Norman P. Jouppi, Sami Yehia:
System-wide performance monitors and their application to the optimization of coherent memory accesses. PPoPP 2005: 247-254 - 2004
- [c36]Norman P. Jouppi:
The Future Evolution of High-Performance Microprocessors. HiPC 2004: 5 - [c35]Jacob Augustine, Shivarama Rao, Norman P. Jouppi, Subu Iyer:
Region of interest editing of MPEG-2 video streams in the compressed domain. ICME 2004: 559-562 - [c34]Norman P. Jouppi, Subu Iyer, Wayne Mack, April Slayden Mitchell, Stan Thomas:
A First Generation Mutually-Immersive Mobile Telepresence Surrogate with Automatic Backtracking. ICRA 2004: 1670-1675 - [c33]Rakesh Kumar, Dean M. Tullsen, Parthasarathy Ranganathan, Norman P. Jouppi, Keith I. Farkas:
Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance. ISCA 2004: 64-75 - [c32]Rakesh Kumar, Norman P. Jouppi, Dean M. Tullsen:
Conjoined-Core Chip Multiprocessing. MICRO 2004: 195-206 - [c31]Norman P. Jouppi, Subu Iyer, Stan Thomas, April Slayden:
BiReality: mutually-immersive telepresence. ACM Multimedia 2004: 860-867 - 2003
- [j13]Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen:
Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures. IEEE Comput. Archit. Lett. 2 (2003) - [c30]Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen:
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. MICRO 2003: 81-92 - 2002
- [c29]Norman P. Jouppi, Wayne Mack, Subu Iyer, Stan Thomas, April Slayden:
First steps towards mutually-immersive mobile telepresence. CSCW Videos 2002: 1 - [c28]Norman P. Jouppi:
First steps towards mutually-immersive mobile telepresence. CSCW 2002: 354-363 - [c27]M. S. Hrishikesh, Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, Norman P. Jouppi, Keith I. Farkas:
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays. ISCA 2002: 14-24 - 2000
- [c26]Bob McNamara, Joel McCormack, Norman P. Jouppi:
Prefiltered Antialiased Lines Using Half-Plane Distance Functions. Workshop on Graphics Hardware 2000: 77-86 - [c25]Parthasarathy Ranganathan, Sarita V. Adve, Norman P. Jouppi:
Reconfigurable caches and their application to media processing. ISCA 2000: 214-224
1990 – 1999
- 1999
- [j12]Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic:
The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning. Int. J. Parallel Program. 27(5): 327-356 (1999) - [j11]Norman P. Jouppi, John Wawrzynek:
Real products, real technology Guest Editor's Introduction]. IEEE Micro 19(2): 10-11 (1999) - [j10]Joel McCormack, Bob McNamara, Chris Gianos, Norman P. Jouppi, Todd A. Dutton, John H. Zurawski, Larry Seiler, Kenneth W. Correll:
Implementing Neon: a 256-bit graphics accelerator. IEEE Micro 19(2): 58-69 (1999) - [c24]Norman P. Jouppi, Chun-Fa Chang:
Z3: An Economical Hardware Technique for High-Quality Antialiasing and Transparency. Workshop on Graphics Hardware 1999: 85-94 - [c23]Parthasarathy Ranganathan, Sarita V. Adve, Norman P. Jouppi:
Performance of Image and Video Processing with General-Purpose Processors and Media ISA Extensions. ISCA 1999: 124-135 - [c22]Joel McCormack, Ronald N. Perry, Keith I. Farkas, Norman P. Jouppi:
Feline: Fast Elliptical Lines for Anisotropic Texture Mapping. SIGGRAPH 1999: 243-250 - 1998
- [c21]Joel McCormack, Bob McNamara, Chris Gianos, Larry Seiler, Norman P. Jouppi, Kenneth W. Correll:
Neon: A Single-Chip 3D Workstation Graphics Accelerator. Workshop on Graphics Hardware 1998: 123-132 - [c20]Norman P. Jouppi:
Retrospective: Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers. 25 Years ISCA: Retrospectives and Reprints 1998: 71-73 - [c19]Norman P. Jouppi:
Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache Prefetch Buffers. 25 Years ISCA: Retrospectives and Reprints 1998: 388-397 - 1997
- [c18]Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic:
Memory-System Design Considerations for Dynamically-Scheduled Processors. ISCA 1997: 133-143 - [c17]Subbarao Palacharla, Norman P. Jouppi, James E. Smith:
Complexity-Effective Superscalar Processors. ISCA 1997: 206-218 - [c16]Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic:
The Multicluster Architecture: Reducing Cycle Time Through Partitioning. MICRO 1997: 149-159 - 1996
- [j9]Norman P. Jouppi, Stefanos Sidiropoulos, Suresh Menon:
A speed, power, and supply noise evaluation of ECL driver circuits. IEEE J. Solid State Circuits 31(1): 38-45 (1996) - [j8]Steven J. E. Wilton, Norman P. Jouppi:
CACTI: an enhanced cache access and cycle time model. IEEE J. Solid State Circuits 31(5): 677-688 (1996) - [c15]Keith I. Farkas, Norman P. Jouppi, Paul Chow:
Register File Design Considerations in Dynamically Scheduled Processors. HPCA 1996: 40-51 - 1995
- [c14]Keith I. Farkas, Norman P. Jouppi, Paul Chow:
How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors? HPCA 1995: 78-89 - 1994
- [j7]Norman P. Jouppi, Patrick D. Boyle, John S. Fitch:
Designing, packaging, and testing a 300-MHz, 115 W ECL microprocessor. IEEE Micro 14(2): 50-58 (1994) - [c13]Norman P. Jouppi, Steven J. E. Wilton:
Tradeoffs in Two-Level On-Chip Caching. ISCA 1994: 34-45 - [c12]Keith I. Farkas, Norman P. Jouppi:
Complexity/Performance Tradeoffs with Non-Blocking Loads. ISCA 1994: 211-222 - 1993
- [c11]Norman P. Jouppi:
Cache Write Policies and Performance. ISCA 1993: 191-201 - 1992
- [c10]J. Bradley Chen, Anita Borg, Norman P. Jouppi:
A Simulation Based Study of TLB Performance. ISCA 1992: 114-123 - 1991
- [j6]John L. Hennessy, Norman P. Jouppi:
Computer Technology and Architecture: An Evolving Interaction. Computer 24(9): 18-29 (1991) - 1990
- [c9]Norman P. Jouppi:
Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers. ISCA 1990: 364-373
1980 – 1989
- 1989
- [j5]Norman P. Jouppi, Jeffrey Y.-F. Tang:
A 20-MIPS sustained 32-bit CMOS microprocessor with high ratio of sustained to peak performance. IEEE J. Solid State Circuits 24(5): 1348-1359 (1989) - [j4]Norman P. Jouppi:
The Nonuniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance. IEEE Trans. Computers 38(12): 1645-1658 (1989) - [c8]Norman P. Jouppi, Jonathan Bertoni, David W. Wall:
A Unified Vector/Scalar Floating-Point Architecture. ASPLOS 1989: 134-143 - [c7]Norman P. Jouppi, David W. Wall:
Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines. ASPLOS 1989: 272-282 - [c6]Norman P. Jouppi:
Integration and packaging plateaus of processor performance. ICCD 1989: 229-232 - [c5]Norman P. Jouppi:
Architectural and Organizational Tradeoffs in the Design of the MultiTitan CPU. ISCA 1989: 281-289 - 1988
- [j3]Norman P. Jouppi:
Superscalar vs. superpipelined machines. SIGARCH Comput. Archit. News 16(3): 71-80 (1988) - 1987
- [j2]Norman P. Jouppi:
Derivation of Signal Flow Direction in MOS VLSI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(3): 480-490 (1987) - [j1]Norman P. Jouppi:
Timing Analysis and Performance Improvement of MOS VLSI Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(4): 650-665 (1987) - 1983
- [c4]Norman P. Jouppi:
Timing analysis for nMOS VLSI. DAC 1983: 411-418 - 1982
- [c3]John L. Hennessy, Norman P. Jouppi, Forest Baskett, Thomas R. Gross, John Gill:
Hardware/Software Tradeoffs for Increased Performance. ASPLOS 1982: 2-11 - [c2]John L. Hennessy, Norman P. Jouppi, John Gill, Forest Baskett, Alex Strong, Thomas R. Gross, Christopher Rowen, Judson S. Leonard:
The MIPS Machine. COMPCON 1982: 2-7 - [c1]John L. Hennessy, Norman P. Jouppi, Steven A. Przybylski, Christopher Rowen, Thomas R. Gross, Forest Baskett, John Gill:
MIPS: A microprocessor architecture. MICRO 1982: 17-22
Coauthor Index
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